在 VHDL 中开发可控时钟分频器

Question

我从 1khz（周期为 1ms）的起始时钟频率开始，并有一个端口变量指定周期的最小步长，它由我的 FPGA 板上的开关控制。例如-

如何实现控制价值除数。计数变量大小的值取决于引用开关输入值的开关情况。到目前为止，这是我尝试实施的：

library ieee;
use ieee.std_logic_1164.all;

entity clk_div is
    generic (      
        NUM_OF_SWS      :   INTEGER RANGE   1 TO 16 := 16   -- Number of input switches
        );
    port (
        sw      :   IN  STD_LOGIC_VECTOR(NUM_OF_SWS-1 downto 0);
        clkin   : in std_logic;
        reset   : in std_logic;
        clkout  : out std_logic
        );
end entity clk_div;

architecture behav of clk_div is
signal clkint : std_logic;        -- Clkint is the internal clock (output), but as you know, you cannot read an output signal...
shared variable step : integer;
signal count : integer range 0 to step-1;
begin
    
    process (sw)    
    begin
    case (sw) is
        when "0000000000000001" => step := 2;
        when "0000000000000100" => step := 3;
        when "0000000000001000" => step := 4;
        when "0000000000010000" => step := 5;
        when "0000000000100000" => step := 6;
        when "0000000001000000" => step := 7;
        when "0000000010000000" => step := 8;
        when "0000000100000000" => step := 9;
        when "0000001000000000" => step := 10;
        when "0000010000000000" => step := 11;
        when "0000100000000000" => step := 12;
        when "0001000000000000" => step := 13;
        when "0010000000000000" => step := 14;
        when "0100000000000000" => step := 15;
        when "1000000000000000" => step := 16;
        when others => step := 1;         
    end case;
end process;

    process (clkin, reset, clkint)
    
    begin       
        if reset = '1' then
            count <= 0;
            clkint <= '0';
        
        elsif rising_edge(clkin) then           
            if count >= step-1 then              
                clkint <= not clkint;    
                count <= 0;                      -- If we're at the top we toggle the output clock and restart counting...
            else
                count <= count + 1;              -- We are not at the top so increment the counter
            end if;
        end if;     
        clkout <= clkint;
    end process;
end behav;