VHDL 断言 - 并发语句

Question

我正在尝试使用 VHDL 断言。在我的设计中，我直接在 DUT 中编写了断言语句，因为我想监视内部信号。由于我的断言与指令同时发生，模拟器几乎在每次输入更改时都会发出报告。

我在下面给你一个最小的工作示例（一个简单的加法器）。这不是我的实际设计，只是我的问题的一个说明。

如何修改我的代码，以便断言不会在不需要的时候触发？这里没有合成限制。

提前谢谢您！

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity Full_Adder is
   port( X, Y, Cin : in std_logic;
         sum, Cout : out std_logic);
end Full_Adder;
 
architecture bhv of Full_Adder is

signal s_sum : std_logic:='0'; -- to be used in the assert
signal s_Cout : std_logic:='0'; -- to be used in the assert

begin

   s_sum <= (X xor Y) xor Cin;
   s_Cout <= (X and (Y or Cin)) or (Cin and Y);
   sum<=s_sum;
   Cout<=s_Cout;

   assert (s_sum =((X xor Y) xor Cin)) report "Erreur de somme" severity note;
   assert (s_Cout = ((X and (Y or Cin)) or (Cin and Y))) report "Erreur de retenue" severity note;

end bhv;

测试台：

Library IEEE;
USE IEEE.Std_logic_1164.all;
entity tb_fulladder is
end tb_fulladder;
 
architecture behavioral of tb_fulladder is
 component Full_Adder
   port( 
   X, Y, Cin : in std_logic;  
  sum, Cout : out std_logic
  );  
 end component; 

 signal A,B,Cin: std_logic:='0';
 signal S,Cout: std_logic;

begin   
 structural_adder: Full_Adder port map 
   (
    X => A,
    Y => B,
    Cin => Cin,
    sum => S,
    Cout => Cout 
   );
   
process
  begin
   A <= '0';
   B <= '0';
   Cin <= '0';
   wait for 100 ns;
   A <= '0';
   B <= '0';
   Cin <= '1';
   wait for 100 ns;   
   A <= '0';
   B <= '1';
   Cin <= '0';
   wait for 100 ns;
   A <= '0';
   B <= '1';
   Cin <= '1';
   wait for 100 ns;
   A <= '1';
   B <= '0';
   Cin <= '0';
   wait for 100 ns;
   A <= '1';
   B <= '0';
   Cin <= '1';
   wait for 100 ns;
   A <= '1';
   B <= '1';
   Cin <= '0';
   wait for 100 ns;   
   A <= '1';
   B <= '1';
   Cin <= '1';
   wait for 100 ns;   
  end process;
      
end behavioral;

Answer 1

您可以在流程结构中编写断言，其敏感度列表可用于控制信号，如下所示；

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity Full_Adder is
   port( X, Y, Cin : in std_logic;
         sum, Cout : out std_logic);
end Full_Adder;
 
architecture bhv of Full_Adder is

signal s_sum : std_logic:='0'; -- to be used in the assert
signal s_Cout : std_logic:='0'; -- to be used in the assert

begin

   s_sum <= (X xor Y) xor Cin;
   s_Cout <= (X and (Y or Cin)) or (Cin and Y);
   sum<=s_sum;
   Cout<=s_Cout;

   process(<related signals>) begin
      assert (s_sum =((X xor Y) xor Cin)) report "Erreur de somme" severity note;
      assert (s_Cout = ((X and (Y or Cin)) or (Cin and Y))) report "Erreur de retenue" severity note;
   end process;

end bhv;