[在vivado中调用模块时发生语法错误

Question

[在xilinx vivado中实现以下代码时，调用子模块时发生语法错误

FA5,FD2,fc2,com1,com2,com3  

除了模块FA4，FD1和fc1。

所有子模块均已测试，并且工作正常。如何调整MAU模块以正确调用给定模块？

module MAU(clk,reset,Nmax,error_tol,omega,error,result);

input clk,reset;
input Nmax,error_tol,omega;
output error,result;

wire[15:0] Nmax,error_tol,omega,result;
reg[15:0] a,b,aplusb,c,zero,n;
wire[15:0] fc1,fc2,fc_out;
wire FA4,FA5,FD1,FD2,com1,com2,com3;
reg [15:0] bigNum1,bigNum2,bigNum3;
integer error;

always@*
begin
a<=16'b0000000000000000;   //initial value of a
b<=16'b0111110000000000;   //initial value of b
n<=16'b0111110000000000;   //initial value of n
zero<=16'b0000000000000000;//loading the value of zero
end

begin                    //finding the initial C and fc_out
float_adder FA4(.num1(a),.num2(b),.result(aplusb));   //finding initial a+b
float_divider FD1(.num(aplusb),.result(c));           //finding initial c
fc_value fc1(.omega(omega),.x(c),.fc_out(fc_out));    //find  iniitial fc_out
end


always@*
begin
while ((bigNum1[15:0]==fc_out[15:0]) |(bigNum2[15:0]==Nmax[15:0]))  //consider two conditions

n <= n + 1'b1;

comparator com3(.num1(fc_out),.num2(zero),.bigNum(bigNum3));          //compare and output big value from fc_out and zero 

if(fc_out[15:0]==bigNum3[15:0])//considering the condition

  begin
  assign a=c;
  end

else
 begin
 assign b=c;
 end


  begin                    //updating C and fc_out
  float_adder FA5(.num1(a),.num2(b),.result(aplusb));   //updating a+b
  float_divider FD2(.num(aplusb),.result(c));           //updating c
  fc_value fc2(.omega(omega),.x(c),.fc_out(fc_out));    //updating fc_out


 comparator com1(.num1(fc_out),.num2(error_tol),.bigNum(bigNum1)); //compare and output big value from fc_out & error_tol
 comparator com2(.num1(Nmax),.num2(n),.bigNum(bigNum2));           //compare and output big value from Nmax and n
  end

end

 always@*
 if (bigNum1 != fc_out)

  begin
  assign error = 0 ;
  end

 else
  begin 
  assign error = 1 ;
  end


assign result = c;




endmodule

Answer 1

1. 我认为您应该使用电线，而不是在调用模块输出中使用寄存器；
2. 在始终阻止之外调用它；
3. 不要在被叫模块的两个输出端口中使用同一根电线；
4. 在总是块的设计中使用clk；