如何在verilog中编写有符号数？

Question

我想编写一个 verilog 代码，输出 2 个 8 位 2 的补码有符号整数的和。另一个二进制输出信号称为 E，当最终结果出现上溢或下溢时，该信号会升高。

但是当我的测试平台为负数（有符号）时，它就会变成无符号整数。

例如，(-23)base 10 有符号 (11101001)base 2 有符号，变成 (233)base 10 (11101001)base 2 无符号。

//ripple_adder.v
module Full_Adder (A, B, carry_in, sum, carry_out);
    input signed A, B;
    input signed carry_in;
    output signed sum;
    output carry_out;

    assign sum = (A^B^carry_in);
    assign carry_out = ((A&B) | (B&carry_in) | (carry_in&A));
endmodule

module ripple_adder (A, B, carry_in, sum, carry_out, E);
    input signed [7:0] A;
    input signed [7:0] B;
    input carry_in;
    output signed [7:0] sum;
    output carry_out;
    output E;
    wire [6:0] carry;

    Full_Adder FA0(A[0], B[0], carry_in, sum[0], carry[0]);
    Full_Adder FA1(A[1], B[1], carry_in, sum[1], carry[1]);
    Full_Adder FA2(A[2], B[2], carry_in, sum[2], carry[2]);
    Full_Adder FA3(A[3], B[3], carry_in, sum[3], carry[3]);
    Full_Adder FA4(A[4], B[4], carry_in, sum[4], carry[4]);
    Full_Adder FA5(A[5], B[5], carry_in, sum[5], carry[5]);
    Full_Adder FA6(A[6], B[6], carry_in, sum[6], carry[6]);
    Full_Adder FA7(A[7], B[7], carry_in, sum[7], carry_out);

    assign E = ((carry_out & ~carry[6]) | (~carry_out & carry[6]));

endmodule

//ripple_adder_tb.v
// testbench module
`timescale 1ps/1ps
`include "coba.v"

module cobatb;
  reg signed [7:0] A, B;
  reg carry_in;
  wire signed [7:0] S;
  wire carry_out;
  wire E;

  ripple_adder uut (
    .A(A),
    .B(B),
    .carry_in(carry_in),
    .sum(S),
    .carry_out(carry_out),
    .E(E)
  );

  initial begin
    $dumpfile("cobatb.vcd");
    $dumpvars(0, cobatb);

    // Test 1
    A = 5;
    B = 10;
    carry_in = 0;
    #10;

    // Test 2
    A = 87;
    B = -23;
    carry_in = 0;
    #10;

    // Test 3
    A = -120;
    B = 60;
    carry_in = 0;
    #10

    // Test 4
    A = -80;
    B = -64;
    carry_in = 0;
    #10

    // Additional tests...
    $display("Test is complete");
    $finish;
  end
endmodule

如何将有符号的 2 的补码整数放入 verilog 测试平台中

Answer 1

我运行了你的测试平台并打印了 B 值。

    // Test 1
    A = 5;
    B = 10;
    carry_in = 0;
    $display("B = %0d",B);
    #10;

    // Test 2
    A = 87;
    B = -23;
    carry_in = 0;
    $display("B = %0d",B);
    #10;

    // Test 3
    A = -120;
    B = 60;
    carry_in = 0;
    $display("B = %0d",B);
    #10

    // Test 4
    A = -80;
    B = -64;
    carry_in = 0;
    $display("B = %0d",B);
    #10

它产生

xcelium> run
B = 10
B = -23
B = 60
B = -64
Test is complete

似乎 verilog 正在将这些值视为有符号的，这是我所期望的，因为您已将它们声明为有符号的。