因此,我试图在我的整个文件中的 VHDL 中实现单周期 MIPS 处理器,我试图签署扩展其中一行,但是我收到错误 10500(错误(10500):mipsoverall.vhd(57)处的 VHDL 语法错误)靠近文本“others”;需要“(”或标识符(“others”是保留关键字)或一元运算符
我正在排除故障的第 57 行:
extended_input <= ((sig_instr(15)=>others(31 downto 16)) & (sig_instr(15 downto 0)));
这是代码,请告诉我我的方向是否正确或者是否需要进行其他更改
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mips_overall is
port (clk,reset: in std_logic;
instruction: in std_logic_vector(31 downto 0);
result: out std_logic_vector(31 downto 0));
end mips_overall;
architecture behavior of mips_overall is
component reg is
port (source_1,source_2,destination: in std_logic_vector(4 downto 0);
write_d: in std_logic_vector(31 downto 0);
reset,clk,en_write: in std_logic;
data_1,data_2: out std_logic_vector(31 downto 0));
end component;
component instr_mem is
port (address: in std_logic_vector(31 downto 0);
reset,clk: in std_logic;
instruction: out std_logic_vector(31 downto 0));
end component;
component counter is
port (increment: in std_logic_vector(31 downto 0);
reset,clk: in std_logic;
count: out std_logic_vector(31 downto 0));
end component;
component ALU is
port (input1,input2: in std_logic_vector(31 downto 0);
clk: in std_logic;
ALUcontrol: in std_logic_vector(3 downto 0);
beqzero: out std_logic;
result: out std_logic_vector(31 downto 0));
end component;
component datamem is
port (address,write_data: in std_logic_vector(31 downto 0);
clk,reset,store_en,load_en: in std_logic;
read_data: out std_logic_vector(31 downto 0));
end component;
signal sig_source1, sig_source2, sig_dest: std_logic_vector(4 downto 0);
signal sig_write_d, sig_data1, sig_data2: std_logic_vector(31 downto 0);
signal sig_instr_address, sig_instr: std_logic_vector(31 downto 0);
signal sig_increment, sig_count: std_logic_vector(31 downto 0);
signal sig_input1, sig_input2, sig_result: std_logic_vector(31 downto 0);
signal sig_alucontrol: std_logic_vector(3 downto 0);
signal sig_beqzero: std_logic;
signal sig_data_address, sig_data_write_data, sig_data_read_data: std_logic_vector(31 downto 0);
signal sig_en_store,sig_en_load,sig_en_write: std_logic; --enables connect direcly to control
signal extended_input: std_logic_vector(31 downto 0); --extended signal
signal mux1,mux2,mux3: std_logic:= '0';--control signal for mux
begin
sig_source1<=sig_instr(25 downto 21);
sig_source2<=sig_instr(20 downto 16);
sig_input1<=sig_data1;
extended_input <= ((sig_instr(15)=>others(31 downto 16)) & (sig_instr(15 downto 0)));
process(mux1,mux2,mux3)
begin
if (mux1='0') then
sig_dest<=sig_instr(20 downto 16);
elsif (mux1='1') then
sig_dest<=sig_instr(15 downto 11);
end if;
if (mux3='0') then
sig_write_d<=sig_data_read_data;
elsif (mux3='1') then
sig_write_d<=sig_result;
end if;
if (mux2='0') then
sig_input2<=sig_data2;
elsif (mux2='1') then
sig_input2<=extended_input;
end if;
end process;
reg_inst : reg
port map (source_1 => sig_source1,
source_2 => sig_source2,
destination => sig_dest,
write_d => sig_write_d,
reset => reset,
clk => clk,
en_write => sig_en_write,
data_1 => sig_data1,
data_2 => sig_data2);
instr_mem_inst : instr_mem
port map ( address => sig_instr_address,
reset => reset,
clk => clk,
instruction => sig_instr);
counter_inst : counter
port map (increment => sig_increment,
reset => reset,
clk => clk,
count => sig_count);
ALU_inst : ALU
port map (input1 => sig_input1,
input2 => sig_input2,
clk => clk,
ALUcontrol => sig_alucontrol,
beqzero => sig_beqzero,
result => sig_result);
datamem_inst : datamem
port map (address => sig_data_address,
write_data => sig_data_write_data,
clk => clk,
reset => reset,
store_en => sig_en_store, -- Connect signals
load_en => sig_en_load, -- Connect signals
read_data => sig_data_read_data);
end behavior;
符号扩展代码未按预期工作我试图使用指令的 MSB 并使用其他指令来填充其余位。谢谢您的帮助。
这里的问题来自于作业中
others
的错误使用。 others
用于将特定数组的所有值(或剩余的未分配位)分配给相同的值。 Others
不能有数组约束。您需要定义一个聚合,然后分配其他聚合。因此,在您的情况下,您希望前 16 位作为符号位。像这样:
extended_input <= (31 downto 16 => (others => sig_instr(15)) & sig_instr(15 downto 0);
此处,通过定义一个具有
31 downto 16
范围的数组并将所有位分配为 sig_instr
的符号位来形成聚合。
您最好使用
signed
包中的 numeric_std
类型,然后您可以使用调整大小功能:
signal extended_input : signed(31 downto 0);
...
extended_input <= resize( signed(sig_instr(15 downto 0)), extended_input'length) );
resize
函数可以为您进行符号扩展。
您对聚合符号的使用是错误的(有关语法,请参阅您最喜欢的 VHDL 书籍)。根据您的情况,您可以尝试:
extended_input(15 downto 0) <= sig_instr(15 downto 0);
extended_input(31 downto 16) <= (others => sig_instr(15));
或者,当您使用
ieee.numeric_std
时:
extended_input <= std_logic_vector(resize(u_signed(sig_instr(15 downto 0)), 32));
签名扩展由
ieee.numeric_std.resize
函数实现,签名为:
function RESIZE (ARG : UNRESOLVED_SIGNED; NEW_SIZE : NATURAL) return UNRESOLVED_SIGNED;
这就是为什么我们在这里需要两次类型转换:
u_signed(sig_instr(15 downto 0))
从 std_logic_vector
转换为 UNRESOLVED_SIGNED
(u_signed
是 UNRESOLVED_SIGNED
的较短别名)std_logic_vector(...)
将结果转换回 std_logic_vector
。注意:您应该使用
std_ulogic_vector
和 std_ulogic
(未解析类型),而不是 std_logic_vector
和 std_logic
(前者的已解析子类型)。您不希望在您的情况下解析类型。如果您不理解其中的差异,请始终使用未解析的类型(这就是 u
中 std_ulogic
的含义),直到有一天,您确实需要一个已解析的类型,这是有充分理由的。
在任何地方默认使用解析类型就像没有降落伞跳跃一样。可能有些人(教授、经理……)或工具要求您默认使用解析类型。尝试抵制(但不要因此被解雇),他们错了,可能也不理解其中的区别。