car_parking_system。我在模拟程序时遇到问题。这是描述停车场系统的程序

Question

我的程序有问题。当密码==2'b10或2'b01时，我的程序状态为WRONG_PASS。但是当我更改密码==2'b11时，状态不是RIGHT_PASS。直到WRONG_PASS为止。请帮助我

module car_parking_system( 
                input clk,reset,
 input sensor_entrance, sensor_exit, 
 input [1:0] password,
 output wire GREEN_LED,RED_LED,YELLOW_LED,output reg [2:0] counter_wait_output,output reg [2:0] number_enter_output ,output led_com
    );
 parameter IDLE = 3'b000, WAIT_PASSWORD = 3'b001, WRONG_PASS = 3'b010, RIGHT_PASS = 3'b011,STOP = 3'b100;
 // Moore FSM : output just depends on the current state
wire ck_1HZ;
assign led_com=1'b1;
 clk_1hz divider_1HZ(clk,ck_1HZ);
 reg[2:0] current_state, next_state;
 reg[32:0] counter_wait;
 reg red,green,yellow;
 reg [2:0] number_enter;
 // Next state
 initial begin 
    number_enter = 0;
    counter_wait = 0;
     end
 always @(posedge ck_1HZ or negedge reset)
 begin
 if(~reset) 
 current_state = IDLE;
 else
 current_state = next_state;
 end
 // counter_wait
 always @(posedge ck_1HZ or negedge reset) 
 begin
 if(~reset) 
 counter_wait <= 0;
 else if(current_state==WAIT_PASSWORD)
 counter_wait <= counter_wait + 1;
 else 
 counter_wait <= 0;
 end
 // change state
// fpga4student.com FPGA projects, Verilog projects, VHDL projects
 always @(*)
 begin
 case(current_state)
 IDLE: begin
         if(sensor_entrance == 1)
 next_state = WAIT_PASSWORD;
 else
 next_state = IDLE;
 end
 WAIT_PASSWORD: begin
 if(counter_wait < 5  && password==2'b11)
 next_state = RIGHT_PASS;
 else if( counter_wait > 5 && password==2'b00)
 next_state=STOP;
 else if (password==2'b01|| password==2'b10)
 next_state =WRONG_PASS;
 else 
 next_state=WAIT_PASSWORD;
 end

WRONG_PASS: begin
  if(password==2'b11) // Correct password after wrong attempts
    next_state = RIGHT_PASS;
  else // Any other password (incorrect or timeout)
    next_state = WRONG_PASS;
  number_enter <= number_enter +1;
end
 
 
 RIGHT_PASS: begin
 if((sensor_entrance==1 && sensor_exit == 1)||number_enter >3 )
 next_state = STOP;
 else if(sensor_exit == 0 && sensor_entrance==0)
 next_state = IDLE;
 else
 next_state = RIGHT_PASS;
 end
 STOP: begin
 if(sensor_entrance==1 && sensor_exit==0)
 next_state = WAIT_PASSWORD;
 else  
 next_state = STOP;
 end
 default: next_state = IDLE;
 endcase
 end
 // LEDs and output, change the period of blinking LEDs here
 always @(*) begin 
 case(current_state)
 IDLE: begin
 green = 1'b0;
 red = 1'b0;
 yellow = 1'b0;

 end
 WAIT_PASSWORD: begin
 green = 1'b0;
 red = 1'b1;
 yellow=1'b0;

 end
 WRONG_PASS: begin
 green = 1'b0;
 red = ~ck_1HZ;
 yellow=1'b0;
 
 end
 RIGHT_PASS: begin
 green = ~ck_1HZ;
 red = 1'b0;
 yellow=1'b0;
 
 end
 STOP: begin
 green = 1'b0;
 red= 1'b0;
 yellow=~ck_1HZ;

 end
 endcase
 end
 
 always @(posedge clk) begin
    counter_wait_output <= counter_wait;
  end
  always @(posedge clk) begin 
  number_enter_output <= number_enter ;
  end
   
 assign RED_LED = red ;
 assign GREEN_LED = green;
 assign YELLOW_LED =yellow;
 endmodule
 
 module clk_1hz (
  input clkht,
  output reg clk
);

  integer d1hz_r;
  integer d1hz_n;
  parameter N = 5   ; 

  initial begin
    d1hz_r = 0;
    d1hz_n = 0;
  end

  always @(posedge clkht) begin
    d1hz_r <= d1hz_n;
  end

  always @* begin
    if (d1hz_r == N) begin
      d1hz_n <= 0;
    end else begin
      d1hz_n <= d1hz_r + 1;
    end
  end

  always @* begin
    clk = (d1hz_r < N/2) ? 1'b1 : 1'b0;
  end
endmodule


////// TEST BENCH 

module tb_car_parking_system;

  // Inputs
  reg clk;
  reg reset;
  reg sensor_entrance;
  reg sensor_exit;
  reg [1:0] password;
  wire [2:0] counter_wait_output;
  wire [2:0] number_enter_output;

  // Outputs
  wire GREEN_LED;
  wire RED_LED;
  wire YELLOW_LED;

  // Instantiate the Unit Under Test (UUT)
  car_parking_system uut (
    .clk(clk), 
    .reset(reset), 
    .sensor_entrance(sensor_entrance), 
    .sensor_exit(sensor_exit), 
    .password(password), 
    .GREEN_LED(GREEN_LED), 
    .RED_LED(RED_LED),
    .YELLOW_LED(YELLOW_LED),
    .counter_wait_output(counter_wait_output),
    .number_enter_output(number_enter_output)
  );

  // Monitor for displaying inputs and outputs
  initial begin
    $monitor("Time=%0t clk=%b reset=%b sensor_entrance=%b sensor_exit=%b password=%b GREEN_LED=%b RED_LED=%b YELLOW_LED=%b counter_wait_output=%b number_enter_output=%b",
             $time, clk, reset, sensor_entrance, sensor_exit, password, GREEN_LED, RED_LED, YELLOW_LED, counter_wait_output, number_enter_output);
  end

  // Clock generation
  initial begin
    clk = 0;
    forever #10 clk = ~clk;
  end

  // Testbench stimulus
  initial begin
    // Initialize Inputs
    reset = 0;
    sensor_entrance = 0;
    sensor_exit = 0;
    password = 0;
    #100;
    reset = 1;
    #20;
    sensor_entrance = 1;
    password = 0;
    #100;
    password = 1;
    #1000;
    password = 2;
    #1000;
    password = 3;
    sensor_entrance = 1;
    // Add stimulus here
  end

endmodule

请帮助我。不知道我哪里做错了。我附上了一个图像，以显示我运行测试台时程序的结果

Answer 1

假设您处于

WAIT_PASSWORD

状态。在这种状态下会发生的是，你的

counter_wait

将开始递增，这是一个

33-bit register

，并且由于你的时钟为 1Hz，因此需要永恒的时间才能溢出。

现在，您将进入

RIGHT_PASS

状态，有两个条件，第一，您的

password==2'b11

，第二，您的

counter_wait

应小于

5

。这就是问题所在，当您处于

WAIT_PASSWORD

状态并且您等待密码变为

2b'11

的时间太长（超过 5 秒，即直到

counter_wait

变得大于或等于

5

）时，您将永远无法再次进入

RIGHT_PASS

状态，并且您将始终处于相同的

WAIT_PASSWORD

状态。

WAIT_PASSWORD: begin
    if(counter_wait < 5  && password==2'b11)
        next_state = RIGHT_PASS;
    else if( counter_wait > 5 && password==2'b00)
        next_state=STOP;
    else if (password==2'b01|| password==2'b10)
        next_state =WRONG_PASS;
    else 
        next_state=WAIT_PASSWORD;
end