我为时钟设置了此代码（12小时），但（am / pm）的一部分不起作用。当小时数从11更改为12时，应从“ AM”更改为“ PM”（反之亦然），其余时间工作正常。我对需要修改的内容一无所知。 FPGA DE1-SOC板当按下“ buttAPM”时，它将在7段显示中显示AM或PM
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Relojf is
port(
clk50_in: in std_logic; --FPGA 50Mhz clock--
buttAPM: in std_logic_vector(0 to 0); --FPGA button,show seconds/letter
rst: in std_logic; --reset-
swu: in std_logic_vector(3 downto 0); --FPGA switch--
swd: in std_logic_vector(2 downto 0); --FPGA switch--
sw9: in std_logic; --FPGA switch--
sw8: in std_logic_vector(0 to 0); --FPGA switch--
buttM: in std_LOGIC; -- set minutes--
buttH: in std_LOGIC; -- set hours---
seg7A: out std_logic_vector(0 to 6); --FPGA 7 segment display--
seg7B: out std_logic_vector(0 to 6); --FPGA 7 segment display--
seg7C: out std_logic_vector(0 to 6); --FPGA 7 segment display--
seg7D: out std_logic_vector(0 to 6); --FPGA 7 segment display--
seg7E: out std_logic_vector(0 to 6); --FPGA 7 segment display--
seg7F: out std_logic_vector(0 to 6); --FPGA 7 segment display--
LED: out std_logic_vector(9 downto 0)
);
end entity;
architecture Behavioral of Relojf is ----sin div
signal auxA: std_logic_vector(0 to 3);----sin div
signal auxB: std_logic_vector(0 to 2);
signal auxC: std_logic_vector(0 to 3):= "0000";
signal auxD: std_logic_vector(0 to 2):= "000";
signal auxE: std_logic_vector(0 to 3):= "0001";
signal auxF: std_logic_vector(0 to 2):= "000";----sin div
signal aux: STD_LOGIC;----divisor 50-1
signal conta : integer range 0 to 24999999 := 0;----divisor 50-1
signal pulse_pass, flag, pol: std_logic;
signal clk_div: std_logic_vector(15 downto 0);
signal duty_cycle: std_logic_vector(9 downto 0);
signal letraM: std_logic_vector(0 to 0):= "0";
signal letrAP: std_logic_vector(0 to 0):= "0";
component pwm is
generic(
max_val: integer := 1000;
val_bits: integer := 10
);
port(
clk50_in: in std_logic;
val_cur: in std_logic_vector((val_bits -1) downto 0);
pulse: out std_logic
);
end component;
begin
LED <= (others => pulse_pass);
process(clk50_in) -- Clock Divide
begin
if(rising_edge(clk50_in)) then
if (clk_div < 49_999) then
clk_div <= clk_div + 1;
flag <= '0';
else
clk_div <= (others => '0');
flag <= '1';
end if;
end if;
end process;
process(clk50_in) -- Duty Cycle
begin
if(rising_edge(clk50_in)) then
if (flag = '1') then -- 1ms Pulse
if (pol = '0') then -- Polarity
if (duty_cycle < 999) then
duty_cycle <= duty_cycle + 1;
pol <= '0';
else
pol <= '1';
end if;
else
if (duty_cycle > 1) then
duty_cycle <= duty_cycle - 1;
pol <= '1';
else
pol <= '0';
end if;
end if;
end if;
end if;
end process;
pwm0: pwm
generic map(
max_val => 1000,
val_bits => 10
)
port map(
clk50_in => clk50_in,
val_cur => duty_cycle,
pulse => pulse_pass
);
process (rst, clk50_in) begin----divisor 50-1
if (rst = '0') then
aux <= '0';
conta <= 0;
elsif rising_edge(clk50_in) then
if (conta = 24999999) then
aux <= NOT(aux);
conta <= 0;
else
conta <= conta + 1;
end if;
end if;
end process;
process (aux,rst) begin
if (rst='0') then
auxA <= (others=>'0');
auxB <= (others=>'0');
auxC <= (others=>'0');
auxD <= (others=>'0');
auxE <= "0001";
auxF <= (others=>'0');
elsif (buttM='0') then
auxC <= swu;
auxD <= swd;
elsif (buttH='0') then
auxE <= swu;
auxF <= swd;
elsif (sw9='1') then
letrAP <= sw8;
elsif(rising_edge(aux)) then
if auxA = "1001" then
auxA <= (others=>'0');
auxB <= auxB + 1;
if auxB = "101" then
auxB <= (others=>'0');
auxC <= auxC + 1;
if auxC = "1001" then
auxC <= "0000";
auxD <= auxD + 1;
if auxD = "101" then
auxD <= "000";
auxE <= auxE + 1;
if auxE = "1001" then
auxE <= "0000";
auxF <= auxF + 1;
if (auxE = "0001" and auxF = "001" and letrAP = "0") then --- apm /
letrAP <= letrAP + 1;
elsif (auxE = "0001" and auxF = "001" and letrAP = "1") then
letrAP <= "0";
end if; ------------------------------------------------------apm--
elsif (auxE = "0010" and auxF = "001") then
auxE <= "0001";
auxF <= "000";
end if;
end if;
end if;
end if;
else
auxA <= auxA + 1;
end if;
end if;
end process;
process (buttAPM) begin
case buttAPM is
when "1" =>
case auxA is
when "0000" => seg7A <= "0000001"; ---0
when "0001" => seg7A <= "1001111"; ---1
when "0010" => seg7A <= "0010010"; ---2
when "0011" => seg7A <= "0000110"; ---3
when "0100" => seg7A <= "1001100"; ---4
when "0101" => seg7A <= "0100100"; ---5
when "0110" => seg7A <= "0100000"; ---6
when "0111" => seg7A <= "0001111"; ---7
when "1000" => seg7A <= "0000000"; ---8
when "1001" => seg7A <= "0000100"; ---9
when others => seg7A <= "1111111"; ---null
end case;
case auxB is
when "000" => seg7B <= "0000001"; ---0
when "001" => seg7B <= "1001111"; ---1
when "010" => seg7B <= "0010010"; ---2
when "011" => seg7B <= "0000110"; ---3
when "100" => seg7B <= "1001100"; ---4
when "101" => seg7B <= "0100100"; ---5
when others => seg7B <= "1111111"; ---null
end case;
when "0" =>
case letraM is
when "0" => seg7A <= "1001000"; ---0
when others => seg7A <= "1111111"; ---null
end case;
case letrAP is
when "0" => seg7B <= "0001000"; ---A
when "1" => seg7B <= "0011000"; ---P
when others => seg7B <= "1111111"; ---null
end case;
end case;
end process;
process (auxC) begin
case auxC is
when "0000" => seg7C <= "0000001"; ---0
when "0001" => seg7C <= "1001111"; ---1
when "0010" => seg7C <= "0010010"; ---2
when "0011" => seg7C <= "0000110"; ---3
when "0100" => seg7C <= "1001100"; ---4
when "0101" => seg7C <= "0100100"; ---5
when "0110" => seg7C <= "0100000"; ---6
when "0111" => seg7C <= "0001111"; ---7
when "1000" => seg7C <= "0000000"; ---8
when "1001" => seg7C <= "0000100"; ---9
when others => seg7C <= "1111111"; ---null
end case;
end process;
process (auxD) begin
case auxD is
when "000" => seg7D <= "0000001"; ---0
when "001" => seg7D <= "1001111"; ---1
when "010" => seg7D <= "0010010"; ---2
when "011" => seg7D <= "0000110"; ---3
when "100" => seg7D <= "1001100"; ---4
when "101" => seg7D <= "0100100"; ---5
when others => seg7D <= "1111111"; ---null
end case;
end process;
process (auxE) begin
case auxE is
when "0000" => seg7E <= "0000001"; ---0
when "0001" => seg7E <= "1001111"; ---1
when "0010" => seg7E <= "0010010"; ---2
when "0011" => seg7E <= "0000110"; ---3
when "0100" => seg7E <= "1001100"; ---4
when "0101" => seg7E <= "0100100"; ---5
when "0110" => seg7E <= "0100000"; ---6
when "0111" => seg7E <= "0001111"; ---7
when "1000" => seg7E <= "0000000"; ---8
when "1001" => seg7E <= "0000100"; ---9
when others => seg7E <= "1111111"; ---null
end case;
end process;
process (auxF) begin
case auxF is
when "000" => seg7F <= "0000001"; ---0
when "001" => seg7F <= "1001111"; ---1
when others => seg7F <= "1111111"; ---null
end case;
end process;
end Behavioral;
您正在尝试在检查letrAP的子句中修改auxE = "1001"。您还有一个附加的内部子句供您分配给letrAP，该子句检查auxE = "0001"。 auxE不能同时为"1001"和"0001"；因此，您的内部子句永远不会求值为TRUE条件，并且永远不会修改letrAP。您必须从内部子句中删除auxE依赖项，因为您已经检查了它是否是"1001"的值。