具有命名关联的总体排序

问题描述 投票:0回答:1

我正在努力理解集合的位顺序,特别是因为我使用了名称关联。

总线被定义为(0 to 3)(3 downto 0),但是由于我使用了命名关联,所以为什么输出z3..0ob3..0彼此相反?为什么outputs_bz_bus相反?与从文字中分配outputs_b相比,为什么从常量数组​​中分配z_bus对位排序有何不同?

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Test_TB is
end entity;

architecture V1 of Test_TB is
    type TLogicLevel is (L, H, X);
    type TOutputs is array(natural range<>) of TLogicLevel;
    type TOutputsTable is array(natural range<>) of TOutputs;

    constant OUTPUTS_TABLE: TOutputsTable :=
    (
        (3 => H,  2 => H,  1 => H,  0 => L),
        (3 => X,  2 => X,  1 => X,  0 => X)  -- Added this because it can't compile an array with a single element.
    );

    signal outputs_a: TOutputs(0 to 3);
    signal outputs_b: TOutputs(3 downto 0);
    signal oa0, oa1, oa2, oa3: TLogicLevel;
    signal ob0, ob1, ob2, ob3: TLogicLevel;

    signal y_bus: TOutputs(0 to 3);
    signal z_bus: TOutputs(3 downto 0);
    signal y0, y1, y2, y3: TLogicLevel;
    signal z0, z1, z2, z3: TLogicLevel;

begin

    process
    begin
        wait for 10 ns;
        y_bus <= (3 => H, 2 => H, 1 => H, 0 => L);              -- Performs bit-for-bit copy.
        z_bus <= (3 => H, 2 => H, 1 => H, 0 => L);              -- Performs bit-for-bit copy. NOT REVERSED.
        outputs_a <= OUTPUTS_TABLE(0);                          -- Performs bit-for-bit copy.
        outputs_b <= OUTPUTS_TABLE(0);                          -- Performs bit-reverse copy. IS REVERSED.
        wait for 10 ns;
        (3 => oa3, 2 => oa2, 1 => oa1, 0 => oa0) <= outputs_a;  -- Performs bit-for-bit copy.
        (3 => ob3, 2 => ob2, 1 => ob1, 0 => ob0) <= outputs_b;  -- Performs bit-reverse copy of a reverse copy, i.e. reverse reverse.
        wait for 10 ns;
        (3 => y3, 2 => y2, 1 => y1, 0 => y0) <= y_bus;          -- Performs bit-for-bit copy.
        (3 => z3, 2 => z2, 1 => z1, 0 => z0) <= z_bus;          -- Performs bit-reverse copy of non-reverse copy. So z3..0 is the reverse of ob3..0.
        wait;
    end process;

end architecture;

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vhdl aggregates
1个回答
0
投票

您的代码行为符合我的预期。

signal y_bus: TOutputs(0 to 3);
signal z_bus: TOutputs(3 downto 0);
...
y_bus <= (3 => H, 2 => H, 1 => H, 0 => L);  
z_bus <= (3 => H, 2 => H, 1 => H, 0 => L); 

对于y_bus,左手位是0,您已将其设置为L。对于z_bus,左手位是3,您已将其设置为H。检查。

constant OUTPUTS_TABLE: TOutputsTable :=
(
    (3 => H,  2 => H,  1 => H,  0 => L),
...
signal outputs_a: TOutputs(0 to 3);
signal outputs_b: TOutputs(3 downto 0);
....
outputs_a <= OUTPUTS_TABLE(0);
outputs_b <= OUTPUTS_TABLE(0); 

对于OUTPUTS_TABLE(0),左手位是0,您已将其设置为L。对于outputs_a,左手位是0,因此您希望它是L。对于outputs_b,左手位是3,因此您希望它是L。检查。

signal outputs_a: TOutputs(0 to 3);
signal outputs_b: TOutputs(3 downto 0);
...
(3 => oa3, 2 => oa2, 1 => oa1, 0 => oa0) <= outputs_a;
(3 => ob3, 2 => ob2, 1 => ob1, 0 => ob0) <= outputs_b;

对于outputs_a,左手位是0,因此您希望oa0L,因为它是左手边的那个。对于outputs_b,左手位是3,因此您希望ob0L,因为那是左手边的那个。校验。但是等等,为什么oa0ob0在左侧?因为这是对聚合(3 => oa3, 2 => oa2, 1 => oa1, 0 => oa0)(3 => ob3, 2 => ob2, 1 => ob1, 0 => ob0)中的位进行编号的方式,因为索引类型将是integerinteger类型的计数。

signal y_bus: TOutputs(0 to 3);
signal z_bus: TOutputs(3 downto 0);
....
y_bus <= (3 => H, 2 => H, 1 => H, 0 => L); 
z_bus <= (3 => H, 2 => H, 1 => H, 0 => L); 
....
(3 => y3, 2 => y2, 1 => y1, 0 => y0) <= y_bus;
(3 => z3, 2 => z2, 1 => z1, 0 => z0) <= z_bus;

因此,我们已经知道,对于y_bus,左手位是0,您将其设置为L;对于z_bus,左手位是3,您将其设置为[ C0]。因此,您希望H(左手位)为y0L(左手位)为z0。检查。

我的头很痛。

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