VHDL“此处不允许使用非共享变量声明”

Question

我有此代码本质上可以计算2个数字的模

library IEEE;

use ieee.numeric_bit.all;

entity resto is
    port (clock , reset : in bit ;
        inicio : in bit ;
        fim : out bit ;
        dividendo , divisor : in bit_vector (15 downto 0) ;
        resto : out bit_vector (15 downto 0)
    ) ;
    end resto;

architecture processo of resto is
    variable    dividendovar : integer range 0 to  15;
    begin

    process(clock, reset) is
    begin
        if reset = '1' then
            fim <= '0';
            resto <= "0000000000000000";
        elsif clock'event and clock = '1' and inicio = '1' then
            dividendovar <= to_integer(unsigned(dividendo));
                if (divisor = "0000000000000000") then
                    -- report "zero"; 
                    resto <= dividendo;
                    fim <= '1';
                elsif (dividendovar = to_integer(unsigned(divisor))) then
                    -- report "menor"; 
                    -- report "dividendoaux vale "& integer'image(to_integer(unsigned(dividendoaux))) ; 
                    resto <= "0000000000000000";
                    fim <= '1';
                elsif (to_integer(unsigned(dividendo)) < to_integer(unsigned(divisor))) then
                    resto <= dividendo;
                    fim <= '1';
                else -- comeca a subtrair
                    while (dividendovar > to_integer(unsigned(divisor))) loop
                        dividendovar := dividendovar - to_integer(unsigned(divisor));
                    end loop ;
                    resto <= bit_vector(to_unsigned(dividendovar, resto'length));
                    fim <= '1';
                end if;
            end if;
            end process;
end architecture;

但是在线

variable    dividendovar : integer range 0 to  15;

我遇到此错误“此处不允许使用非共享变量声明”。

关于我在做什么错或失踪的任何线索？

提前感谢！

Answer 1

变量应在process中声明，因此具有受限范围。

library IEEE;

use ieee.numeric_bit.all;

entity resto is
    port (clock , reset : in bit ;
        inicio : in bit ;
        fim : out bit ;
        dividendo , divisor : in bit_vector (15 downto 0) ;
        resto : out bit_vector (15 downto 0)
    ) ;
    end resto;

architecture processo of resto is
    begin

    process(clock, reset) is
    variable    dividendovar : integer range 0 to  15;
    begin
        if reset = '1' then
            fim <= '0';
            resto <= "0000000000000000";
        elsif clock'event and clock = '1' and inicio = '1' then
            dividendovar <= to_integer(unsigned(dividendo));
                if (divisor = "0000000000000000") then
                    -- report "zero"; 
                    resto <= dividendo;
                    fim <= '1';
                elsif (dividendovar = to_integer(unsigned(divisor))) then
                    -- report "menor"; 
                    -- report "dividendoaux vale "& integer'image(to_integer(unsigned(dividendoaux))) ; 
                    resto <= "0000000000000000";
                    fim <= '1';
                elsif (to_integer(unsigned(dividendo)) < to_integer(unsigned(divisor))) then
                    resto <= dividendo;
                    fim <= '1';
                else -- comeca a subtrair
                    while (dividendovar > to_integer(unsigned(divisor))) loop
                        dividendovar := dividendovar - to_integer(unsigned(divisor));
                    end loop ;
                    resto <= bit_vector(to_unsigned(dividendovar, resto'length));
                    fim <= '1';
                end if;
            end if;
            end process;
end architecture;

如评论中所述，全局共享变量在VHDL2002标准之前可用。我认为，如果仍然需要，应该立即保护它们。但是到目前为止，我较新遇到了一个需要变量的用例。

无论如何，在我所有的设计中，我还是比signals更喜欢variables。