如何基于VHDL编写循环延时文件？

Question

最近在Vivado写了一段代码，vhdl。我想在每次使用该程序时使循环更长（即'num'）。但是我只能做常量。我怎么能做这个循环？

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL ;

entity delay is
--generic(
--  num :  integer:= 5  --Sets the number of cycles to delay
--   );
    Port ( clock : in STD_LOGIC;
           sig   : in std_logic;
           count : in integer;
           delay : out STD_LOGIC);
end delay;

architecture Behavioral of delay is

constant num: integer:= count;
signal sig_delay: std_logic_vector(num-1 downto 0) := (others =>'0');

begin
    process(clock)
    begin
        if (clock = '1') then
            sig_delay(0) <= sig;
            sig_delay(num-1 downto 1) <= sig_delay(num-2 downto 0);
        end if; 
    end process;
    delay <= sig_delay(num-1);

end Behavioral;

谢谢和问候！