无法通过有限状态机 (FSM) 使用有线连接来正确连接模块

问题描述 投票：0回答：1

我的项目本质上是一个歌曲播放器，它实际上并不输出声音，而是在 Basys 3 FPGA 7 段显示器上使用标志按照指定的时序输出音符（即 A、G、D、B）。

我目前一直在尝试在顶部模块中实现 FSM 来决定显示哪些歌曲音符。我制作 Song1.v 模块只是为了看看是否可以显示其中一首歌曲的音符。显示器总是直接进入默认状态，即关闭状态，我尝试使用板载 LED 灯来检查 Song1.v 模块是否正在更新其自己的状态机和 LED[11]，连接到 IDLE 状态，从不打开。这告诉我缺乏连接，但我已经尝试过

我真的陷入困境，希望了解如何使用任何可能的方法来解决它！

`timescale 1ns / 1ps
/////////////////////////////////////////////////////////////////////////////// 
// Authored by David J Marion aka FPGA Dude
// Created on 4/29/2022
/////////////////////////////////////////////////////////////////////////////// 

module song_top(
    input clk_100MHz,       // from Basys 3
    input play,             // btnC
    input next,             // btnR
    input reset,            // btnD
    output [6:0] seg,
    output [3:0] an,
    output reg [15:0] led
    );
    
    localparam IDLE = 2'b00;
    localparam SONG1 = 2'b01;
    localparam SONG2 = 2'b10;
    
    reg [1:0] curr_state = IDLE;
    reg [1:0] next_state;
    
    reg play_song1 = 1'b0;
    reg play_song2 = 1'b0;
   
    wire w_play, w_next, w_reset;
    wire [11:0] w_freq;
    wire w_play_song1;
  
    
    btn_debouncer btnC_play (.clk(clk_100MHz), .btn_in(play), .btn_out(w_play));
    btn_debouncer btnR_next (.clk(clk_100MHz), .btn_in(next), .btn_out(w_next));
    btn_debouncer btnR_reset (.clk(clk_100MHz), .btn_in(reset), .btn_out(w_reset));
    
    song1 s1 (.clk_100MHz(clk_100MHz), .en_song1(w_play_song1), .freq_to_disp(w_freq));
    
    display disp (.freq(w_freq), .segOut(seg), .anode(an));
    
    always @(posedge clk_100MHz) begin
        if(reset) begin
            curr_state = IDLE;
        end 
        else begin
            curr_state = next_state;
        end
        led[0] <= (curr_state == IDLE);
        led[1] <= (curr_state == SONG1);
        led[2] <= (curr_state == SONG2);
        led[3] <= w_reset; // Can show reset status
        led[8] <= play_song1;
    end
    
    always @(*) begin
        next_state = curr_state;
        case (curr_state)
        
            IDLE: begin
                play_song1 <= 1'b0;
                play_song2 <= 1'b0;
                if (w_play) next_state = SONG1;
            end
            
            SONG1: begin
                play_song1 <= 1'b1;
                play_song2 <= 1'b0;
                if (w_next) next_state = SONG2;
                else if (w_reset) next_state = IDLE;
            end
            
            SONG2: begin
                play_song1 <= 1'b0;
                play_song2 <= 1'b1;
                if (w_next) next_state = SONG1;
                else if (w_reset) next_state = IDLE;
            end
        endcase
    end
    
    assign w_play_song1 = play_song1;    
    assign w_play_song2 = play_song2;
    
endmodule

`timescale 1ns / 1ps

// Smoke on the Water by Deep Purple
// guitar riff sequence: G minor
//G, Bb, C
//G, Bb, Db, C
//G, Bb, C
//Bb, G

//G4: 391.995 Hz
//Bb4: 466.164 Hz
//C4: 261.626 Hz
//Db4 (also known as C#4): 277.183 Hz

module song1(
    input clk_100MHz,
    input en_song1,
    output reg [15:0] led,
    output freq_to_disp
    );
   
    localparam IDLE = 4'b0000;
    localparam N1   = 4'b0001;
    localparam N2   = 4'b0010;
    localparam N3   = 4'b0011;
    localparam N4   = 4'b0100;
    localparam N5   = 4'b0101;
    localparam N6   = 4'b0110;
    localparam N7   = 4'b0111;
    localparam N8   = 4'b1000;
    localparam N9   = 4'b1001;
    localparam N10  = 4'b1010;
    localparam N11  = 4'b1011;
    localparam N12  = 4'b1100;
    localparam B1   = 4'b1101;
    localparam B2   = 4'b1110;
    
    
    reg [3:0] curr_note = IDLE;
    reg [3:0] next_note;
     
    wire G, Bb, C, Db;
//    // Instantiate tone modules

    
    parameter CLK_FREQ = 100_000_000;     
    // Timing for Smoke on the Water by Deep Purple
    parameter integer D_260ms = 0.26000000 * CLK_FREQ;  // 260ms
    // Note Break Delay
    parameter integer D_br260 = 0.26000000 * CLK_FREQ;  // 260ms BREAK
    
    reg [25:0] count = 26'b0;
    reg counter_clear = 1'b0;
    
    // note duration Smoke on the Water
    reg flag_260ms = 1'b0;
     // note breaks Smoke on the Water
    reg flag_br260 = 1'b0;
    reg en_song1_prev = 1'b0;
    
    always @(posedge clk_100MHz) begin
        en_song1_prev <= en_song1; // Track the previous state of en_song1
        if (!en_song1 && en_song1_prev) begin
            curr_note <= IDLE;
        end else if (en_song1 && !en_song1_prev) begin
            curr_note <= N1; // Move to N1 only on rising edge of en_song1
        end
        led[11] <= (curr_note == IDLE);
        led[12] <= (curr_note == N1);
        led[13] <= (curr_note == N2);
        led[14] <= (curr_note == N3);
        led[15] <= en_song1;
    end
    
    always @(*) begin
        next_note = curr_note;
            case (curr_note)
            N1: begin
                if (flag_260ms) begin
                    counter_clear = 1;
                    next_note = N2;  // Directly specify next state
                end
            end
            N2: begin
                if (flag_260ms) begin
                    counter_clear = 1;
                    next_note = N3;
                end
            end
            N3: begin
                if (flag_260ms) begin
                    counter_clear = 1;
                    next_note = B1;
                end
            end
            B1: begin
                if (flag_br260) begin
                    counter_clear = 1;
                    next_note = N4;
                end
            end
            N4: begin
                if (flag_260ms) begin
                    counter_clear = 1;
                    next_note = N5;
                end
            end
            N5: begin
                if (flag_260ms) begin
                    counter_clear = 1;
                    next_note = N6;
                end
            end
            N6: begin
                if (flag_260ms) begin
                    counter_clear = 1;
                    next_note = N7;
                end
            end
            N7: begin
                if (flag_260ms) begin
                    counter_clear = 1;
                    next_note = B2;
                end
            end
            B2: begin
                if (flag_br260) begin
                    counter_clear = 1;
                    next_note = N8;
                end
            end
            // Continue defining transitions for N8 to N12, and loop back to N1
            N8: begin
                if (flag_260ms) begin
                    counter_clear = 1;
                    next_note = N9;
                end
            end
            N9: begin
                if (flag_260ms) begin
                    counter_clear = 1;
                    next_note = N10;
                end
            end
            N10: begin
                if (flag_260ms) begin
                    counter_clear = 1;
                    next_note = N11;
                end
            end
            N11: begin
                if (flag_260ms) begin
                    counter_clear = 1;
                    next_note = N12;
                end
            end
            N12: begin
                if (flag_260ms) begin
                    counter_clear = 1;
                    next_note = N1;  // Loop back to the start
                end
            end
        endcase
    end
    //        assign freq_to_disp = (note == "n1" || note == "n4" || note == "n8" || note == "n12") ? 391 : 
//        (note == "n2" || note == "n5" || note == "n9" || note =="n11") ? 466 :
//        (note == "n3" || note == "n7" || note == "n10") ? 261 :
//        (note == "n6") ? 277 : 0;
        
    assign freq_to_disp = (curr_note == N1 || curr_note == N4 || curr_note == N8 || curr_note == N12) ? 391 :
                          (curr_note == N2 || curr_note == N5 || curr_note == N9 || curr_note == N11) ? 466 :
                          (curr_note == N3 || curr_note == N7 || curr_note == N10) ? 261 :
                          (curr_note == N6) ? 277 : 0;
endmodule    


`timescale 1ns / 1ps

// Module which displays the current note being played to the
// 7-segment display
module display(freq, anode, segOut);
    input [11:0] freq;
    output [3:0] anode;     // Controls the display digits
    output [6:0] segOut;    // Controls which digit to display
    
    // Output wires and registers
    wire [3:0] anode;
    reg [6:0] segOut;
    
    // Only display the rightmost digit
    assign anode = 4'b1110;
    
    // NEED TO UPDATE VALUES ACCORDINGLY
    always @(freq) begin
        case (freq)                     // Musical notes:
            523 : segOut <= 7'b1000110; // C
            494 : segOut <= 7'b0000011; // B
            466 : segOut <= 7'b0000011; // *B'b'*
            440 : segOut <= 7'b0001000; // A
            391 : segOut <= 7'b0010000; // *G*
            349 : segOut <= 7'b0001110; // F
            330 : segOut <= 7'b0000110; // E
            294 : segOut <= 7'b0100001; // D
            277 : segOut <= 7'b0100001; // *D'b'*
            261 : segOut <= 7'b1000110; // *C*
            247 : segOut <= 7'b0000011; // B
            220 : segOut <= 7'b0001000; // A
            196 : segOut <= 7'b0010000; // G
            175 : segOut <= 7'b0001110; // F
            165 : segOut <= 7'b0000110; // E
            147 : segOut <= 7'b0100001; // D
            131 : segOut <= 7'b1000110; // C
            default : segOut <= 7'b1111111;
        endcase
    end
endmodule

`timescale 1ns / 1ps

module btn_debouncer(
    input clk,
    input btn_in,
    output btn_out
    );
    
    reg t0, t1, t2;
    
    always @(posedge clk) begin
        t0 <= btn_in;
        t1 <= t0;
        t2 <= t1;
    end
    
    assign btn_out = t2;
    
endmodule

## Clock signal
set_property PACKAGE_PIN W5 [get_ports clk_100MHz]                          
    set_property IOSTANDARD LVCMOS33 [get_ports clk_100MHz]
    create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk_100MHz]
    
## Switches
#set_property PACKAGE_PIN V17 [get_ports {sw[0]}]                   
#   set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
#set_property PACKAGE_PIN V16 [get_ports {sw[1]}]                   
#   set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
#set_property PACKAGE_PIN W16 [get_ports {sw[2]}]                   
#   set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
#set_property PACKAGE_PIN W17 [get_ports {sw[3]}]                   
#   set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
#set_property PACKAGE_PIN W15 [get_ports {sw[4]}]                   
#   set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
#set_property PACKAGE_PIN V15 [get_ports {sw[5]}]                   
#   set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
#set_property PACKAGE_PIN W14 [get_ports {sw[6]}]                   
#   set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
#set_property PACKAGE_PIN W13 [get_ports {sw[7]}]                   
#   set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
#set_property PACKAGE_PIN V2 [get_ports {sw[8]}]                    
#   set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
#set_property PACKAGE_PIN T3 [get_ports {sw[9]}]                    
#   set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
#set_property PACKAGE_PIN T2 [get_ports {sw[10]}]                   
#   set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
#set_property PACKAGE_PIN R3 [get_ports {sw[11]}]                   
#   set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
#set_property PACKAGE_PIN W2 [get_ports {sw[12]}]                   
#   set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
#set_property PACKAGE_PIN U1 [get_ports {sw[13]}]                   
#   set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
#set_property PACKAGE_PIN T1 [get_ports {sw[14]}]                   
#   set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]
#set_property PACKAGE_PIN R2 [get_ports {sw[15]}]                   
#   set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]
 

## LEDs
set_property PACKAGE_PIN U16 [get_ports {led[0]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
set_property PACKAGE_PIN E19 [get_ports {led[1]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
set_property PACKAGE_PIN U19 [get_ports {led[2]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
set_property PACKAGE_PIN V19 [get_ports {led[3]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
set_property PACKAGE_PIN W18 [get_ports {led[4]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
set_property PACKAGE_PIN U15 [get_ports {led[5]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
set_property PACKAGE_PIN U14 [get_ports {led[6]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
set_property PACKAGE_PIN V14 [get_ports {led[7]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
set_property PACKAGE_PIN V13 [get_ports {led[8]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
set_property PACKAGE_PIN V3 [get_ports {led[9]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
set_property PACKAGE_PIN W3 [get_ports {led[10]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
set_property PACKAGE_PIN U3 [get_ports {led[11]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
set_property PACKAGE_PIN P3 [get_ports {led[12]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]
set_property PACKAGE_PIN N3 [get_ports {led[13]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]
set_property PACKAGE_PIN P1 [get_ports {led[14]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]
set_property PACKAGE_PIN L1 [get_ports {led[15]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
    
    
#7 segment display
set_property PACKAGE_PIN W7 [get_ports {seg[0]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]
set_property PACKAGE_PIN W6 [get_ports {seg[1]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
set_property PACKAGE_PIN U8 [get_ports {seg[2]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
set_property PACKAGE_PIN V8 [get_ports {seg[3]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
set_property PACKAGE_PIN U5 [get_ports {seg[4]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
set_property PACKAGE_PIN V5 [get_ports {seg[5]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
set_property PACKAGE_PIN U7 [get_ports {seg[6]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]

#set_property PACKAGE_PIN V7 [get_ports dp]                         
#   set_property IOSTANDARD LVCMOS33 [get_ports dp]

set_property PACKAGE_PIN U2 [get_ports {an[0]}]                 
    set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
set_property PACKAGE_PIN U4 [get_ports {an[1]}]                 
    set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
set_property PACKAGE_PIN V4 [get_ports {an[2]}]                 
    set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
set_property PACKAGE_PIN W4 [get_ports {an[3]}]                 
    set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]


#Buttons
set_property PACKAGE_PIN U18 [get_ports play]                       
    set_property IOSTANDARD LVCMOS33 [get_ports play]
#set_property PACKAGE_PIN T18 [get_ports btnU]                      
#   set_property IOSTANDARD LVCMOS33 [get_ports btnU]
#set_property PACKAGE_PIN W19 [get_ports btnL]                      
#   set_property IOSTANDARD LVCMOS33 [get_ports btnL]
set_property PACKAGE_PIN T17 [get_ports next]                       
    set_property IOSTANDARD LVCMOS33 [get_ports next]
set_property PACKAGE_PIN U17 [get_ports reset]
    set_property IOSTANDARD LVCMOS33 [get_ports reset]                  



#set_property PACKAGE_PIN K3 [get_ports {JXADC[4]}]
    #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}]
##Sch name = XA2_N
#set_property PACKAGE_PIN M3 [get_ports {JXADC[5]}]
    #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}]
##Sch name = XA3_N
#set_property PACKAGE_PIN M1 [get_ports {JXADC[6]}]
    #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}]
##Sch name = XA4_N
#set_property PACKAGE_PIN N1 [get_ports {JXADC[7]}]
    #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}]



##VGA Connector
#set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}]
    #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}]
#set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}]
    #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}]
#set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}]
    #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}]
#set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}]
    #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}]
#set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}]
    #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}]
#set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}]
    #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}]
#set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}]
    #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}]
#set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}]
    #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}]
#set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}]
    #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}]
#set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}]
    #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}]
#set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}]
    #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}]
#set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}]
    #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}]
#set_property PACKAGE_PIN P19 [get_ports Hsync]
    #set_property IOSTANDARD LVCMOS33 [get_ports Hsync]
#set_property PACKAGE_PIN R19 [get_ports Vsync]
    #set_property IOSTANDARD LVCMOS33 [get_ports Vsync]


##USB-RS232 Interface
#set_property PACKAGE_PIN B18 [get_ports RsRx]
    #set_property IOSTANDARD LVCMOS33 [get_ports RsRx]
#set_property PACKAGE_PIN A18 [get_ports RsTx]
    #set_property IOSTANDARD LVCMOS33 [get_ports RsTx]


##USB HID (PS/2)
#set_property PACKAGE_PIN C17 [get_ports PS2Clk]
    #set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk]
    #set_property PULLUP true [get_ports PS2Clk]
#set_property PACKAGE_PIN B17 [get_ports PS2Data]
    #set_property IOSTANDARD LVCMOS33 [get_ports PS2Data]
    #set_property PULLUP true [get_ports PS2Data]


##Quad SPI Flash
##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the
##STARTUPE2 primitive.
#set_property PACKAGE_PIN D18 [get_ports {QspiDB[0]}]
    #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}]
#set_property PACKAGE_PIN D19 [get_ports {QspiDB[1]}]
    #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}]
#set_property PACKAGE_PIN G18 [get_ports {QspiDB[2]}]
    #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}]
#set_property PACKAGE_PIN F18 [get_ports {QspiDB[3]}]
    #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}]
#set_property PACKAGE_PIN K19 [get_ports QspiCSn]
    #set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn]


# Configuration options, can be used for all designs
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
set_property CONFIG_MODE SPIx1 [current_design]
verilog fpga state-machine vivado fsm
1个回答
0
投票

song
模块有一位输出
freq_to_disp

module song1(
    input clk_100MHz,
    input en_song1,
    output reg [15:0] led,
    output freq_to_disp  // 1-bit output
    );

模块

song1
在模块
song_top
中实例化

song1 s1 (.clk_100MHz(clk_100MHz), .en_song1(w_play_song1), .freq_to_disp(w_freq));

如您所见，端口 

freq_to_disp
连接到 
wire w_freq

Wire 

w_freq
是 12 位。

wire [11:0] w_freq;

因此您有一个 12 位信号连接到 1 位端口。

freq_to_disp
上的驱动程序是位向量

    assign freq_to_disp = (curr_note == N1 || curr_note == N4 || curr_note == N8 || curr_note == N12) ? 391 :
                          (curr_note == N2 || curr_note == N5 || curr_note == N9 || curr_note == N11) ? 466 :
                          (curr_note == N3 || curr_note == N7 || curr_note == N10) ? 261 :
                          (curr_note == N6) ? 277 : 0;

设计错误是

song
模块的模块头，
freq_to_disp
端口需要l2位；它在帖子中的一点点。
这就是修复。

module song1(
    input clk_100MHz,
    input en_song1,
    output reg [15:0] led,
    output     [11:0] freq_to_disp  // Change to 11-bit output
    );

我通过将代码粘贴到 www.edaplayground.com 并点击运行来找到此错误，这产生了。

*W,CUVMPW (./design.sv,37|83): port sizes differ in port connection(12/1) for the instance(song_top)

这告诉你上面解释的是什么。

我什至没有写测试平台。

模拟是你的朋友。

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