这是我的 clkdiv26 代码:
ENTITY clkdiv26 IS
PORT(
clk : IN STD_LOGIC;
q2, q1, q0 : OUT STD_LOGIC);
END clkdiv26;
ARCHITECTURE count OF clkdiv26 IS
SIGNAL qd : STD_LOGIC_VECTOR (25 downto 0);
BEGIN
-- Instantiate 4-bit counter
count: lpm_counter
GENERIC MAP (LPM_WIDTH => 26)
PORT MAP ( clock => clk,
q => qd(25 downto 0));
q2 <= qd(25);
q1 <= qd(24);
q0 <= qd(23);
END count;
ENTITY MOD5 IS
PORT(
X, clk : IN STD_LOGIC;
TIMEOUT : OUT STD_LOGIC);
END MOD5;
ARCHITECTURE A of MOD5 is
TYPE STATE_TYPE IS (s0, s1, s2, s3, s4);
SIGNAL state: STATE_TYPE;
BEGIN
PROCESS (clk)
BEGIN
IF clk = '1' THEN
CASE state IS
WHEN s0 =>
state <=S1;
WHEN s1 =>
state <=s2;
WHEN s2 =>
state <=s3;
WHEN s3 =>
state <=s4;
WHEN s4 =>
state <=s0;
END CASE;
END IF;
END PROCESS;
WITH state SELECT
TIMEOUT <='1' WHEN s4,
'0' WHEN s1,
'0' WHEN s2,
'0' WHEN s3,
'0' WHEN s0;
END A;
这是我的 MoD5
我想要它所以输出Q2是MOD5中的X输入,我试过使用组件和端口映射,但它似乎不起作用。有什么想法吗?
我试过端口映射和组件,在启动项目时将clkdiv26文件添加到mod5文件中
当我做端口映射和组件部分时,我总是收到关于声明对象的错误