从寄存器的状态分配 Verilog 输出状态：

Question

我是 Verilog 新手，在 vivado 编程 basys3 板时不断收到此错误：

这是我的 Verilog 代码，它是一个简单的状态机，可以在每个时钟周期更改状态。下面是我的约束文件：

module StateMachine(
output reg[2:0] state, input x, clk, output led0,led1,led2);
 wire sysHardwareClock,scaledClock; 
 parameter S0 = 3'b000, S1 = 3'b001, S2 = 2'b010, S3 = 2'b011, S4 = 2'b100, S5= 3'b101;
 slowClock(sysHardwareClock,scaledClock);
 always @ (posedge scaledClock)
  begin
     case (state)
       S0:state<= S1;
       S1:state<= S2;
      S2:state<= S3;
       S3:state<= S4;
       S4:state<= S5;
       endcase
   end
endmodule


module slowClock(clk, slowclk);
input clk;
output slowclk;

reg slowclk = 1'b0;
reg [27:0] counter;

always@(posedge clk)
  begin
    counter <= counter + 1;
    if ( counter == 25000000)
        begin
          counter <= 0;
         slowclk <= ~slowclk;
    end
  end
endmodule  

约束文件：

## Clock signal
set_property PACKAGE_PIN W5 [get_ports sysHardwareClock]                            
    set_property IOSTANDARD LVCMOS33 [get_ports sysHardwareClock]
    create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports sysHardwareClock]

## LEDs
set_property PACKAGE_PIN U16 [get_ports state[0]]                   
    set_property IOSTANDARD LVCMOS33 [get_ports state[0]]
set_property PACKAGE_PIN E19 [get_ports state[0]]                   
    set_property IOSTANDARD LVCMOS33 [get_ports state[2]]
set_property PACKAGE_PIN U19 [get_ports state[3]]                   
    set_property IOSTANDARD LVCMOS33 [get_ports state[3]]

我尝试将错误更改为警告，但什么也没做

Answer 1

该错误通知您

led0

输出未连接到

StateMachine

模块内的任何内容。所有输出端口应由模块内部的逻辑驱动。

您应该从运行 Verilog 模拟开始，这也会告诉您问题。