我正在 Vivado 中运行 VHDL 仿真。 当我运行它时，它运行到最后并且工作正常。 但是，我得到了错误
FATAL_ERROR：达到迭代限制 9999999。在仿真时间无法提前的情况下检测到可能的零延迟振荡。请检查您的源代码。请注意，可以使用开关 -maxdeltaid 更改迭代限制。
迭代限制是10000，但是因为模拟没有运行到我想要的时间，所以我增加了限制。
我实际上只运行了 100ns，时间分辨率为 1ns。那么我不应该只有 100 的最大迭代吗？当我在 ModelSim 中尝试这些时间时，它运行这些没有任何问题。为什么会有迭代限制？
这些是相关设置：
xsim.elaborate.xelab.more_options* -timeprecision_vhdl 1ns
xsim.simulate.xsim.more_options* -maxdeltaid 9999999
xsim.simulate.runtime* 100ns
这些是 TCL 控制台日志：
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-12493] Simulation top is 'RsFlipFlop_tb'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Vivado Workspace/TestProject/TestProject.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2022.2/tps/boost_1_72_0'
INFO: [SIM-utils-54] Inspecting design source files for 'RsFlipFlop_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Vivado Workspace/TestProject/TestProject.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj RsFlipFlop_tb_vhdl.prj"
INFO: [USF-XSim-69] 'compile' step finished in '4' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Vivado Workspace/TestProject/TestProject.sim/sim_1/behav/xsim'
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot RsFlipFlop_tb_behav xil_defaultlib.RsFlipFlop_tb -log elaborate.log -timeprecision_vhdl 100ps"
Vivado Simulator v2022.2
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2022.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot RsFlipFlop_tb_behav xil_defaultlib.RsFlipFlop_tb -log elaborate.log -timeprecision_vhdl 100ps
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Vivado Workspace/TestProject/TestProject.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "RsFlipFlop_tb_behav -key {Behavioral:sim_1:Functional:RsFlipFlop_tb} -tclbatch {RsFlipFlop_tb.tcl} -log {simulate.log} -maxdeltaid 9999999"
INFO: [USF-XSim-8] Loading simulator feature
Time resolution is 100 ps
source RsFlipFlop_tb.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 100ns
FATAL_ERROR: Iteration limit 9999999 is reached. Possible zero delay oscillation detected where simulation time can not advance. Please check your source code. Note that the iteration limit can be changed using switch -maxdeltaid.
Time: 50 ns Iteration: 9999999
run: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1074.465 ; gain = 0.000
xsim: Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1074.465 ; gain = 0.000
INFO: [USF-XSim-96] XSim completed. Design snapshot 'RsFlipFlop_tb_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 100ns
launch_simulation: Time (s): cpu = 00:00:12 ; elapsed = 00:00:19 . Memory (MB): peak = 1074.465 ; gain = 0.000
任何人都可以向我解释什么是错的，如果有什么错的话？ 非常感谢您！