添加功能覆盖以发送条件信号

Question

我是system-verilog中功能覆盖的新手。当两个信号不相等时，我想写一个封面组。

例如，我对每个信号都有两个独立的覆盖范围。

    covergroup group1 @(posedge `TB_TOP.clk); 
    cpb_1 : coverpoint `TB_TOP.sig1 {
        bins r_zero = {0};
        bins r_one = {1};
     endgroup
    covergroup group2 @(posedge `TB_TOP.clk); 
    cpb_2 : coverpoint `TB_TOP.sig2 {
        bins r_zero = {0};
        bins r_one = {1};
     endgroup

现在我想在sig1不等于sig2时添加另一个时钟。谢谢

Answer 1

你的意思是这样的？

covergroup group3 @(posedge `TB_TOP.clk);
  // coverpoint can take an expression, so provide sig1!=sig2
  cpb_3: coverpoint (`TB_TOP.sig1 != `TB_TOP.sig2) {
    // Since we only want to cover this case, sample a true value (1) only
    bins covered = {1};
  }
endgroup