在VHDL中用modelsim编程加法器时出错

Question

错误：C：/Users/username/dir1/dir2/sumador_modelo.vhd（11）：在“ NOT”附近：（vcom-1576）期望'）'。

错误：C：/Users/username/dir1/dir2/sumador_modelo.vhd（12）：VHDL编译器正在退出。

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY sumador_modelo IS
   PORT (a,b,Cin:IN STD_LOGIC; sum,Cout:OUT STD_LOGIC);
END sumador_modelo;

ARCHITECTURE sumador_modelo_flujo OF sumador_modelo IS
    BEGIN   
    sum<=(NOT a AND NOT b AND Cin) OR (NOT  a AND b AND NOT Cin) OR (a AND NOT b AND NOT Cin) OR (a AND b AND Cin); 
    Cout<=(NOT a AND b AND Cin) OR (a AND NOT b AND Cin) OR (a AND b NOT Cin) OR (a AND b AND Cin);
END sumador_modelo_flujo;

Answer 1

您在“ not”之前缺少“和”：

sum<=(NOT a AND NOT b AND Cin) OR (NOT  a AND b AND NOT Cin) OR (a AND NOT b AND NOT Cin) OR (a AND b AND Cin); 
Cout<=(NOT a AND b AND Cin) OR (a AND NOT b AND Cin) OR (a AND b and NOT Cin) OR (a AND b AND Cin);