UVM 只创建顶层? [关闭]

问题描述 投票:0回答:1

UVM新手需要你的帮助。

环境:VCS-2018.06 uvm-1.1d ubuntu-18.06

当我参考MENTOR的代码通过uvm验证mgc_uart ip时,我发现在debug的路上总是报出Null object access的错误,尽管它们确实存在。于是我在uart_test的mian_phase中调用了uvm_top.print_topology()来打印整个UVM结构,就在这时我发现了神奇的场景,uvm结构只有uart_test。

VCS 编译成功并生成 SIMV 文件,没有任何错误。

使用 ./simv 运行任何测试时都会出现此问题

the result in ubuntu 根据我对 uvm 的经验,所有 build_phase 都应该首先执行 正常情况下,应该是这样的: the right one

我哪里可能出错了?

1.注释掉apb_protocol_moniter中最后一个封面

  1. 现在你得到错误-[NOA]空对象访问

  2. 在uart_test_base中注释int_vseq()

  3. 问题,只创建了uart_test,没有创建其他结构体

这是我的代码的一部分:

m_env_cfg.m_modem_agent_cfg = m_modem_cfg;
  m_env                       = uart_env::type_id::create("m_env", this);
  uvm_config_db#(uart_env_config)::set(this, "m_env.*", "uart_env_config", m_env_cfg);
  uvm_config_db#(uart_env_config)::set(this, "m_env.*", "cfg", m_env_cfg);

endfunction : build_phase

function void uart_test_base::init_vseq(uart_vseq_base vseq);
  assert (m_env != null);
  // vseq.apb            = m_env.m_apb_agent.m_sequencer;
  // vseq.uart           = m_env.m_rx_uart_agent.m_uart_sequencer;
  // vseq.modem          = m_env.m_modem_agent.m_sequencer;
  // vseq.rm             = rm;
  // vseq.tx_uart_config = m_tx_uart_cfg;
  // vseq.rx_uart_config = m_rx_uart_cfg;
  // vseq.cfg            = m_env_cfg;

env 存在,但其内部组件不存在。对其内部的任何引用都将报告为空对象访问,例如:m_env.m_apb_agent m_env.m_modem_agent.m_sequencer。但是它们应该被创建并存在

这是 env 的一些代码:

function void uart_env::build_phase(uvm_phase phase);
  `uvm_info("uart_env","build_phase",UVM_LOW);
  if (!uvm_config_db#(uart_env_config)::get(this, "", "uart_env_config", m_cfg)) begin
    `uvm_error("build_phase", "Unable to get uart_env_config from uvm_config_db")
  end
  m_apb_agent = apb_agent::type_id::create("m_apb_agent", this);
  uvm_config_db #(apb_agent_config)::set(this, "m_apb_agent*", "apb_agent_config", m_cfg.m_apb_agent_cfg);
  m_tx_uart_agent = uart_agent::type_id::create("m_tx_uart_agent", this);
  uvm_config_db #(uart_agent_config)::set(this, "m_tx_uart_agent*", "uart_agent_config", m_cfg.m_tx_uart_agent_cfg);
  m_rx_uart_agent = uart_agent::type_id::create("m_rx_uart_agent", this);
  uvm_config_db #(uart_agent_config)::set(this, "m_rx_uart_agent*", "uart_agent_config", m_cfg.m_rx_uart_agent_cfg);
  m_modem_agent = modem_agent::type_id::create("m_modem_agent", this);
  uvm_config_db #(modem_config)::set(this, "m_modem_agent*", "modem_config", m_cfg.m_modem_agent_cfg);
  `uvm_info("uart_env","run here",UVM_LOW);
  reg_predictor = uvm_reg_predictor #(apb_seq_item)::type_id::create("reg_predictor", this);
  reg_adapter = reg2apb_adapter::type_id::create("reg_adapter");
  // Analysis components:
  tx_sb         = uart_tx_scoreboard::type_id::create("tx_sb", this);
  rx_sb         = uart_rx_scoreboard::type_id::create("rx_sb", this);
  modem_sb      = uart_modem_scoreboard::type_id::create("modem_sb", this);
  tx_cov        = uart_tx_coverage_monitor::type_id::create("tx_cov", this);
  rx_cov        = uart_rx_coverage_monitor::type_id::create("rx_cov", this);
  int_cov       = uart_interrupt_coverage_monitor::type_id::create("int_cov", this);
  modem_cov     = uart_modem_coverage_monitor::type_id::create("modem_cov", this);
  br_sb         = baud_rate_checker::type_id::create("br_sb", this);
  reg_cov       = uart_reg_access_coverage_monitor::type_id::create("reg_cov", this);
endfunction : build_phase

它们没有被构造,看起来uvm没有调用它们的build_phase。这很奇怪。

它们都包含 build_phase 和新函数:

 function new(string name = "modem_agent", uvm_component parent = null);
    super.new(name, parent);
  endfunction

  extern function void build_phase(uvm_phase phase);
  extern function void connect_phase(uvm_phase phase);
endclass : modem_agent

function void modem_agent::build_phase(uvm_phase phase);
  `uvm_info("modem_agent", "build_phase", UVM_LOW);
  ap        = new("modem_agent_ap", this);
  m_monitor = modem_monitor::type_id::create("monitor", this);
  if (!uvm_config_db#(modem_config)::get(this, "", "modem_config", cfg)) `uvm_fatal("CONFIG_LOAD", "Cannot get() configuration modem_config from uvm_config_db. Have you set() it?")
  if (cfg.active) begin
    m_driver    = modem_driver::type_id::create("drv", this);
    m_sequencer = modem_sequencer::type_id::create("sequencer", this);
  end
  if (cfg.has_coverage) begin
    m_cov = modem_coverage_monitor::type_id::create("m_cov", this);
  end
  `uvm_info("modem_agent", "build_phase finish", UVM_MEDIUM);
endfunction : build_phase

如何上传项目供爱好者分析?

verilog system-verilog uvm
1个回答
0
投票

你需要在适当的地方写入super.build_phase,然后你就可以看到正确的打印消息。

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