如何使用 VHDL 在 FPGA 上实现洛伦兹系统

Question

我正在尝试为方程式给出的随机密钥生成器编写 4d 洛伦兹系统的 VHDL 代码：

 dx/dt = σ(y − x) ; 
 dy/dt = ρx − y − xz ; 
 dz/dt = βz + xy ; 
 dw/dt = λ(x − w) ; 

我是硬件语言的新手，这似乎很难。我使用了 EULER 方法，并且在每次操作后截断向量以将输出保持在 32 位长度。问题是输出信号的行为不够混乱和随机，无法通过 NIST 测试。 如果有人尝试改进我的代码或告诉我哪里出了问题，我将非常感激我需要一些帮助

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

 entity lorenzSystem is port (
        reset, clock  : in std_logic; 
        
        x_out           : out std_logic_vector(31 downto 0);
        y_out           : out std_logic_vector(31 downto 0); 
        z_out           : out std_logic_vector(31 downto 0);  
        w_out           : out std_logic_vector(31 downto enter image description here0) 

) ;
 end lorenzSystem;

 architecture behavioral of lorenzSystem is
signal t1,t2,t3,t4  : std_logic_vector(127 downto 0);
--- constants ---- 
constant dt    : std_logic_vector(63 downto 0):= X"00000000028f5c29"; -- time step = 0.001 
----parameteres in fixed point hexadecimal ----
constant a     : std_logic_vector(31 downto 0):= X"000a0000"; ----10
constant b     : std_logic_vector(31 downto 0):= X"001c0000"; ----28
constant c    : std_logic_vector(31 downto 0):= X"0002aaab";--8/3 
constant d     : std_logic_vector(31 downto 0):= X"000f0000";---15
---- initial conditions ----
constant x0    : std_logic_vector(31 downto 0):= X"000019aa";   -- 0.1
constant y0    : std_logic_vector(31 downto 0):= X"000019aa";
constant z0    : std_logic_vector(31 downto 0):= X"000019aa" ; 
constant w0    : std_logic_vector(31 downto 0):= X"000019aa" ; 



 signal x_sig  : std_logic_vector(31 downto 0):=x0;
 signal y_sig  : std_logic_vector(31 downto 0):=y0;
 signal z_sig  : std_logic_vector(31 downto 0):=z0;
 signal w_sig  : std_logic_vector(31 downto 0):=w0;


  begin
-------------------------------------------------------------------------
--------------------------- lorenzsystem---------------------------------
  process(clock, reset)
  begin
  if reset = '1' then
  ---- initial condition when reset = 1 ----
                     x_sig <= x0; 
                     y_sig <= y0; 
                     z_sig <= z0; 
                     w_sig <= w0 ; 
                     
                    
  elsif ( rising_edge(clock) )   then
                               ----- update the value od x, y, z, w ---- 
                                 x_sig <= x_sig + t1 (77 downto 46) ; --x
                                 y_sig <= y_sig + t2 (77 downto 46) ;--y  
                                 z_sig <= z_sig + t3 (77 downto 46) ;--z  
                                 w_sig <= w_sig + t4 (77 downto 46) ;--w                                 
end if ;                            
end process;
---- Euler resolution -----
 t1 <= ( a*(y_sig-x_sig )) *dt ;-- x 
 t2 <= ( x_sig*(b - z_sig) - y_sig ) *dt   ;  -- y 
 t3 <= ( x_sig *y_sig - c*z_sig ) *dt ; --z   
 t4 <= ( d*z_sig - d*w_sig ) *dt ; ---w 
 ------ output -------      
     x_out <=  x_sig  ;   
     y_out <=  y_sig  ;     
     z_out <=  z_sig ;     
     w_out <=  w_sig  ;
-------------------------                       
  end behavioral;