verilog 中的 32 位指令存储器

Question

在指令存储器中，我们需要内部存储器来存储指令。我们需要定义一个 2D 数组存储 64 条指令，每条指令 4 字节（32 位）。因此，将指令存储器定义为一种新类型 这是一个 64 × 32 2D 数组，并从指令存储器类型中定义信号存储器。 然后，我们需要在我们定义的信号中实际存储一些指令（32 位数据） 作为内部存储。

这是我到目前为止所拥有的：

// Module definition
module InstMem (
input [7:2] addr,
output wire [31:0] instruction
);

reg [31:0] memory[63:0];
assign instruction= memory[addr[7:2]];
initial begin
memory[0] = 32'h00007033; // and r0, r0, r0 32'h00000000
memory[1] = 32'h00100093; // addi r1, r0, 1 32'h00000001
memory[2] = 32'h00200113; // addi r2, r0, 2 32'h00000002
memory[3] = 32'h00308193; // addi r3, r1, 3 32'h00000004
memory[4] = 32'h00408213; // addi r4, r1, 4 32'h00000005
memory[5] = 32'h00510293; // addi r5, r2, 5 32'h00000007
memory[6] = 32'h00610313; // addi r6, r2, 6 32'h00000008
memory[7] = 32'h00718393; // addi r7, r3, 7 32'h0000000B
memory[8] = 32'h00208433; // add r8, r1, r2 32'h00000003
memory[9] = 32'h404404b3; // sub r9, r8, r4 32'hfffffffe
memory[10] = 32'h00317533; // and r10, r2, r3 32'h00000000
memory[11] = 32'h0041e5b3; // or r11, r3, r4 32'h00000005
memory[12] = 32'h0041a633; // if r3 is less than r4 then r12 = 1 32'h00000001
memory[13] = 32'h007346b3; // nor r13, r6, r7 32'hfffffff4
memory[14] = 32'h4d34f713; // andi r14, r9, "4D3" 32'h000004D2
memory[15] = 32'h8d35e793; // ori r15, r11, "8d3" 32'hfffff8d7
memory[16] = 32'h4d26a813; // if r13 is less than 32'h000004D2 then r16 = 1 32'h00000000
memory[17] = 32'h4d244893; // nori r17, r8, "4D2" 32'hfffffb2C

end
endmodule 

模块 instr_memtb( reg [7:2} addr; 线 [31:0] 指令; InstMem 即时(.addr(addr),.指令(指令));

initial begin
    addr = 6'b000000; // Initial address (will be overridden by force command in simulation)
    #100; // Simulate for 100 nanoseconds
   
end endmodule

我正在努力保持恒定的力。它获取指令，但 vivado 中的波形配置全是 X 和 0，请帮我解决这个问题！！

Answer 1

16位地址需要调整为模块内的内存寻址。

module InstMem (
  input [7:2] addr,
output wire [31:0] instruction
);

reg [31:0] memory[63:0];
  assign instruction= memory[addr >> 2];
initial begin
memory[0] = 32'h00007033; // and r0, r0, r0 32'h00000000
memory[1] = 32'h00100093; // addi r1, r0, 1 32'h00000001
memory[2] = 32'h00200113; // addi r2, r0, 2 32'h00000002
memory[3] = 32'h00308193; // addi r3, r1, 3 32'h00000004
memory[4] = 32'h00408213; // addi r4, r1, 4 32'h00000005
memory[5] = 32'h00510293; // addi r5, r2, 5 32'h00000007
memory[6] = 32'h00610313; // addi r6, r2, 6 32'h00000008
memory[7] = 32'h00718393; // addi r7, r3, 7 32'h0000000B
memory[8] = 32'h00208433; // add r8, r1, r2 32'h00000003
memory[9] = 32'h404404b3; // sub r9, r8, r4 32'hfffffffe
memory[10] = 32'h00317533; // and r10, r2, r3 32'h00000000
memory[11] = 32'h0041e5b3; // or r11, r3, r4 32'h00000005
memory[12] = 32'h0041a633; // if r3 is less than r4 then r12 = 1 32'h00000001
memory[13] = 32'h007346b3; // nor r13, r6, r7 32'hfffffff4
memory[14] = 32'h4d34f713; // andi r14, r9, "4D3" 32'h000004D2
memory[15] = 32'h8d35e793; // ori r15, r11, "8d3" 32'hfffff8d7
memory[16] = 32'h4d26a813; // if r13 is less than 32'h000004D2 then r16 = 1 32'h00000000
memory[17] = 32'h4d244893; // nori r17, r8, "4D2" 32'hfffffb2C

end
endmodule

测试台

module instr_memtb() ;
  
reg [7:2] addr; 
wire [31:0] instruction; 
  
  
InstMem instant(.addr(addr),.instruction(instruction));

initial begin
  addr = 6'h00; // Initial address (will be overridden by force command in simulation)
  #1;
  $display("ins = %h",instruction);
  addr = 6'h04; // Initial address (will be overridden by force command in simulation)
  #1;
  $display("ins = %h",instruction);
  #1;
  $display("ins = %h",instruction);
end

endmodule

产品

xcelium> run
ins = 00007033
ins = 00100093
ins = 00100093