我正在尝试使用VHDL配置规范进行预设
这应该是可能的,如IEEE1076-2008第7.3.2.1节所示,它给出了以下示例:
entity AND_GATE is
generic (I1toO, I2toO: DELAY_LENGTH := 4 ns);
port (I1, I2: in BIT; O: out BIT);
end entity AND_GATE;
entity XOR_GATE is
generic (I1toO, I2toO: DELAY_LENGTH := 4 ns);
port (I1, I2: in BIT; O: out BIT);
end entity XOR_GATE;
package MY_GATES is
component AND_GATE is
generic (I1toO, I2toO: DELAY_LENGTH := 4 ns);
port (I1, I2: in BIT; O: out BIT);
end component AND_GATE;
component XOR_GATE is
generic (I1toO, I2toO: DELAY_LENGTH := 4 ns);
port (I1, I2: in BIT; O: out BIT);
end component XOR_GATE;
end package MY_GATES;
entity Half_Adder is
port (X, Y: in BIT; Sum, Carry: out BIT);
end entity Half_Adder;
use WORK.MY_GATES.all;
architecture Structure of Half_Adder is
for L1: XOR_GATE use
entity WORK.XOR_GATE(Behavior) -- The primary binding
generic map (3 ns, 3 ns) -- indication for instance L1.
port map (I1 => I1, I2 => I2, O => O);
for L2: AND_GATE use
entity WORK.AND_GATE(Behavior) -- The primary binding
generic map (3 ns, 4 ns) -- indication for instance L2.
port map (I1, open, O);
begin
L1: XOR_GATE port map (X, Y, Sum);
L2: AND_GATE port map (X, Y, Carry);
end architecture Structure;
use WORK.GLOBAL_SIGNALS.all;
configuration Different of Half_Adder is
for Structure
for L1: XOR_GATE
generic map (2.9 ns, 3.6 ns); -- The incremental binding
end for; -- indication of L1; rebinds its generics.
for L2: AND_GATE
generic map (2.8 ns, 3.25 ns) -- The incremental binding
port map (I2 => Tied_High); -- indication of L2; rebinds
end for; -- its generics and binds its open port.
end for;
end configuration Different;
即使我自己添加了示例中缺少的包
package GLOBAL_SIGNALS is
constant Tied_High : bit := '1';
end package GLOBAL_SIGNALS;
在Modelsim中,精化仍然失败。
错误:[...] / half_adder.vhd(36):( vcom-1035)正式端口“I2”具有OPEN或没有实际关联。
由线引起的
port map (I1, open, O);
这似乎表明Modelsim不能正确支持这些配置语句。
我想使用此配置规范来简化我的设计输入。
例:
entity comp is
generic(step : time; defined: boolean);
port(clk, data : in bit);
end entity;
entity e is end entity e;
architecture a of e is
component comp is
generic(step : time; defined: boolean);
port(clk, data : in bit);
end component;
signal clk1, clk2 : bit;
for a : comp use
entity work.comp
generic map(step => 1 ns)
port map(clk => clk1);
for b : comp use
entity work.comp
generic map(step => 100 ns)
port map(clk => clk2);
for all : comp use
entity work.comp
generic map(defined => true);
signal sig_a, sig_b : bit;
begin
a: comp
port map(data => sig_a);
b_gen : for i in 0 to 2 generate
b: comp
port map(data => sig_b);
end generate;
end architecture;
此代码会抛出大量错误:
错误:[...] / e.vhd(19):( vcom-1031)正式通用“已定义”具有OPEN或无实际关联。
错误:[...] / e.vhd(19):( vcom-1035)正式端口“数据”具有OPEN或没有实际关联。
错误:[...] / e.vhd(23):( vcom-1031)正式通用“已定义”具有OPEN或无实际关联。
错误:[...] / e.vhd(23):( vcom-1035)正式端口“数据”具有OPEN或没有实际关联。
错误:[...] / e.vhd(26):( vcom-1031)正式通用“步骤”具有OPEN或没有实际关联它。
错误:[...] / e.vhd(24):组件“comp”的所有配置规范都尝试重新绑定已绑定的实例。
错误:[...] / e.vhd(24):组件“comp”的所有配置规范都尝试重新绑定已绑定的实例。
错误:[...] / e.vhd(32):( vcom-1031)正式通用“步骤”具有OPEN或没有实际关联它。
错误:[...] / e.vhd(32):( vcom-1031)正式通用“已定义”具有OPEN或没有实际关联它。
错误:[...] / e.vhd(32):( vcom-1035)正式端口“clk”具有OPEN或没有实际关联。
错误:[...] / e.vhd(36):( vcom-1031)正式通用“步骤”具有OPEN或没有实际关联它。
错误:[...] / e.vhd(36):( vcom-1031)正式通用“已定义”具有OPEN或没有实际关联。
错误:[...] / e.vhd(36):( vcom-1035)正式端口“clk”具有OPEN或没有实际关联。
警告:[...] / e.vhd(24):( vcom-1263)配置规范“all:comp”不适用于组件实例化语句。
错误:[...] / e.vhd(20):未找到带有标签“b”的陈述。
因此,似乎这不是使用配置规范的受支持方式。太糟糕了,因为它可以简化我的设计入门。
我只是一个Modelsim错误,或者配置规范从未以这种方式帮助这些默认绑定?
问题已经改变,这个答案也是如此。
在Modelsim中,精化仍然失败。
错误:[...] / half_adder.vhd(36):( vcom-1035)正式端口“I2”具有OPEN或没有实际关联。
由线引起的
port map (I1, open, O);
这似乎表明Modelsim不能正确支持这些配置语句。
没有“正确”可以应用于您的结论,VHDL标准不支持。
该错误似乎是由于在未绑定I2时试图详细说明Half_Adder
引起的。配置规范将I2与open
相关联,这是不允许的。
如果你创建一个Minimal, Complete and Verifiable example:
-- IEEE Std 1076-1993 5.2.1 Binding Indication (example)
-- -2008 7.3.2.1
package global_signals is -- THIS PACKAGE MISSING IN THE EXAMPLE
signal Tied_High: bit := '1';
end package;
entity AND_GATE is -- ADDED entity and architecture
generic (I1toO, I2toO: DELAY_LENGTH := 4 ns);
port (I1, I2: in BIT; O: out BIT);
end entity AND_GATE;
architecture Behavior of AND_GATE is -- ADDED
signal In1, In2: BIT;
begin
In1 <= I1 after I1toO;
In2 <= I2 after I2toO;
O <= In1 and In2;
process
begin
report
LF & HT & "I1to0 = " & time'image(I1toO) &
LF & HT & "I2to0 = " & time'image(I2toO);
wait;
end process;
end architecture Behavior;
entity XOR_GATE is -- ADDED entity and architecture
generic (I1toO, I2toO : DELAY_LENGTH := 4 ns);
port (I1, I2: in BIT; O : out BIT);
end entity XOR_GATE;
architecture Behavior of XOR_GATE is -- ADDED
signal In1, In2: BIT;
begin
In1 <= I1 after I1toO;
In2 <= I2 after I2toO;
O <= In1 xor In2;
process
begin
report
LF & HT & "I1to0 = " & time'image(I1toO) &
LF & HT & "I2to0 = " & time'image(I2toO);
wait;
end process;
end architecture Behavior;
package MY_GATES is
component AND_GATE is
generic (I1toO, I2toO: DELAY_LENGTH := 4 ns);
port (I1, I2: in BIT; O: out BIT);
end component AND_GATE;
component XOR_GATE is
generic (I1toO, I2toO: DELAY_LENGTH := 4 ns);
port (I1, I2: in BIT; O : out BIT);
end component XOR_GATE;
end package MY_GATES;
entity Half_Adder is
port (X, Y: in BIT;
Sum, Carry: out BIT);
end entity Half_Adder;
use WORK.MY_GATES.all;
architecture Structure of Half_Adder is
signal O: bit; -- Added
for L1: XOR_GATE use
entity WORK.XOR_GATE(Behavior) -- The primary binding indication
generic map (3 ns, 3 ns) -- for instance L1.
port map (I1 => I1, I2 => I2, O => O);
for L2: AND_GATE use
entity WORK.AND_GATE(Behavior) -- The primary binding indication
-- generic map (3 ns, 4 ns) -- for instance L2.
port map (I1, open, O);
begin
L1: XOR_GATE port map (X, Y, Sum);
L2: AND_GATE port map (X, Y, Carry);
end architecture Structure;
use WORK.GLOBAL_SIGNALS.all;
configuration Different of Half_Adder is
for Structure
for L1: XOR_GATE
generic map (2.9 ns, 3.6 ns); -- The incremental binding
end for; -- indication of L1; rebinds its generics.
for L2: AND_GATE
generic map (2.8 ns, 3.25 ns) -- The incremental binding
port map (I2 => Tied_High); -- indication L2; rebinds its generics
end for; -- and binds its open port.
end for;
end configuration Different;
在这种情况下,它在一个设计文件中进行分析,阐述和模拟:
ghdl -a Half_Adder.vhdl ghdl -e不同 ghdl -r不同 Half_Adder.vhdl:44:9:@ 0ms :(报告说明):I1to0 = 2900000 fs I2to0 = 3600000 fs Half_Adder.vhdl:22:9:@ 0ms :(报告说明):I1to0 = 2800000 fs I2to0 = 3250000 fs
同时演示代码函数中表达的增量绑定。
请注意,这需要从包含最近Github提交的源代码构建的ghdl实现。
提交:9e0cf4af3cf2141002b37db9803c15afec8ea2f4 [9e0cf4a] 父母:b801510561 作者:特里斯坦金戈尔德 日期:2017年10月30日上午7:19:41 GMT + 13
分析,详细说明和运行上述Half_Adder需要在2017年10月30日之后从Github存储库构建的ghdl,能够在最近恢复的应用语义分析的变化中意外丢失。释放时,该功能将在ghdl-0.35中。
没有人注意到缺乏一段时间的几年。与增量绑定的作者可能希望的相比,该功能可能不那么热情。您还可以注意到标准中的示例不完整,并且在以后的修订版中出现了其他拼写错误。 MCVe现已纳入ghdl的测试套件中。
您生成的第二个示例代码(e.vhdl)未提供配置声明。
附件一(资料性)词汇表
增量绑定:配置声明中的绑定指示,用于重新关联先前关联的本地通用常量或关联先前未关联的本地端口,称为递增重新绑定绑定指示适用的组件实例。 (7.3.2.1)
这种“限制”是如何产生的,是语义要求的问题。
Jean-MichelBergé,Alain Fonkoua,Serge Maginot和Jacques Rouillard在“VHDL'92”一书的作者中可以了解增量约束。参见VHDL'92,6。增量装订,第47至56页。
(增量绑定也可以在IEEE Std P1076-1992c中找到,并随后被并入IEEE Std 1076-1993修订版中)。
您的第二个示例中存在各种语义缺陷:
e.vhdl:
entity comp is
generic(step : time; defined: boolean);
port(clk, data : in bit);
end entity;
entity e is end entity e;
architecture a of e is
component comp is
generic(step : time; defined: boolean);
port(clk, data : in bit);
end component;
signal clk1, clk2 : bit;
for a : comp use -- Line 15
entity work.comp
generic map(step => 1 ns)
port map(clk => clk1);
for b : comp use -- Line 20
entity work.comp
generic map(step => 100 ns)
port map(clk => clk2);
for all : comp use -- Line 24
entity work.comp
generic map(defined => true);
signal sig_a, sig_b : bit;
begin
a: comp -- Line 31
port map(data => sig_a);
b_gen : for i in 0 to 2 generate
b: comp -- Line 35
port map(data => sig_b);
end generate;
end architecture;
除了缺少配置声明之外,该示例通过Modelsim错误和警告以及ghdl演示了这些缺点:
ghdl -a e.vhdl e.vhdl:31:5:error: no actual for constant interface "step" e.vhdl:35:9:error: no actual for constant interface "step" e.vhdl:20:9:error: no component instantation with label "b" e.vhdl:24:5:error: component instance "a" is already bound by a configuration specification e.vhdl:16:5:error: (previous is configuration specification) ghdl:error: compilation error
综合工具通常支持配置规范,但不支持配置声明。当应用于用于硅的设计时,增量绑定没有实际用途。