Verilog临时变量

Question

我试图在Verilog中进行CMP指令。为了保持减法的结果，我声明了一条线。这就是代码的样子（在always语句中执行）。

wire [data_width:0] tmp_wire = reg_accumulator - reg_x;

f_zero <= tmp_wire & 'hFF == 0;
f_carry <= tmp_wire & 'h100;

现在，Icarus Verilog抱怨语法错误，并且reg_accumulator - reg_x不是l-value：

cpu.v:149: syntax error
cpu.v:149: Syntax in assignment statement l-value.

为什么会抱怨？在函数/任务中声明临时变量的正确方法是什么？

module comparator(
    input clk,
    input [7:0] op_a,
    input [7:0] op_b
);

reg f_zero;
reg f_carry;

function compare;
    input [data_width-1:0] a;
    input [data_width-1:0] b;
begin
    wire [7:0] tmp_wire = reg_accumulator - reg_x;

    f_zero <= tmp_wire & 'hFF == 0;
    f_carry <= tmp_wire & 'h100;
end
endfunction

always @(posedge clk) begin
    compare(op_a, op_b);
end

endmodule // comparator

Answer 1

您无法在wire块中声明always。

wire [7:0] tmp_wire = reg_accumulator - reg_x;

always @(posedge clk) begin
    f_zero <= tmp_wire & 'hFF == 0;
    f_carry <= tmp_wire & 'h100;
end