根据结果，synthis的verilog代码是否可行？ （你是如何确定 synthis 是否可行的？）
想看可以综合的RTL代码，但是tcl代码有没有多余的部分？
如果你正在写RTL代码是否可以综合的报告，应该展示哪一部分？
我正在编写 i2s 代码，有没有我需要添加的功能？
i2s_top.v
module i2s_top #(
parameter AUDIO_DW = 16
)(
input i_tx_sclk,
input i_rst_n,
input [AUDIO_DW-1:0] i_tx_prescaler,
input [AUDIO_DW-1:0] i_tx_left_chan,
input [AUDIO_DW-1:0] i_tx_right_chan,
output [AUDIO_DW-1:0] o_rx_left_chan,
output [AUDIO_DW-1:0] o_rx_right_chan
);
wire w_sclk;
wire w_lrclk;
wire w_sdata;
i2s_tx #(
.AUDIO_DW(AUDIO_DW)
) i2s_tx (
.i_tx_sclk(i_tx_sclk),
.i_tx_rst_n(i_rst_n),
.i_tx_prescaler(i_tx_prescaler),
.o_tx_sclk(w_sclk),
.o_tx_lrclk(w_lrclk),
.o_tx_sdata(w_sdata),
.i_tx_left_chan(i_tx_left_chan),
.i_tx_right_chan(i_tx_right_chan)
);
i2s_rx #(
.AUDIO_DW(AUDIO_DW)
) i2s_rx (
.i_rx_sclk(w_sclk),
.i_rx_rst_n(i_rst_n),
.i_rx_lrclk(w_lrclk),
.i_rx_sdata(w_sdata),
.o_rx_left_chan(o_rx_left_chan),
.o_rx_right_chan(o_rx_right_chan)
);
endmodule
i2s_tx.v
module i2s_tx #(
parameter AUDIO_DW = 16
)(
input i_tx_sclk,
input [AUDIO_DW-1:0] i_tx_prescaler,
input i_tx_rst_n,
output wire o_tx_sclk,
output reg o_tx_lrclk = 0,
output reg o_tx_sdata = 0,
input [AUDIO_DW-1:0] i_tx_left_chan,
input [AUDIO_DW-1:0] i_tx_right_chan
);
reg [AUDIO_DW-1:0] tx_bit_cnt;
reg [AUDIO_DW-1:0] tx_left;
reg [AUDIO_DW-1:0] tx_right;
assign o_tx_sclk = i_tx_sclk;
always @(negedge i_tx_sclk or negedge i_tx_rst_n) begin
if (!i_tx_rst_n) begin
tx_bit_cnt <= 1;
tx_left <= 0;
tx_right <= 0;
end else begin
if (tx_bit_cnt >= i_tx_prescaler) begin
tx_bit_cnt <= 1;
end else begin
tx_bit_cnt <= tx_bit_cnt + 1;
end
if (tx_bit_cnt == i_tx_prescaler && o_tx_lrclk) begin
tx_left <= i_tx_left_chan;
tx_right <= i_tx_right_chan;
end
o_tx_lrclk <= (tx_bit_cnt == i_tx_prescaler) ? ~o_tx_lrclk : o_tx_lrclk;
o_tx_sdata <= o_tx_lrclk ? tx_right[AUDIO_DW - tx_bit_cnt] : tx_left[AUDIO_DW - tx_bit_cnt];
end
end
endmodule
i2s_rx.v
module i2s_rx #(
parameter AUDIO_DW = 16
)(
input i_rx_sclk,
input i_rx_rst_n,
input i_rx_lrclk,
input i_rx_sdata,
output reg [AUDIO_DW-1:0] o_rx_left_chan = 0,
output reg [AUDIO_DW-1:0] o_rx_right_chan = 0
);
reg [AUDIO_DW-1:0] rx_left = 0;
reg [AUDIO_DW-1:0] rx_right = 0;
reg rx_lrclk_r = 0;
wire rx_lrclk_nedge;
assign rx_lrclk_nedge = !i_rx_lrclk & rx_lrclk_r;
always @(posedge i_rx_sclk or negedge i_rx_rst_n)
if (!i_rx_rst_n) begin
rx_lrclk_r <= 0;
rx_left <= 0;
end else if (rx_lrclk_r) begin
rx_right <= {rx_right[AUDIO_DW-2:0], i_rx_sdata};
end else
rx_left <= {rx_left[AUDIO_DW-2:0], i_rx_sdata};
always @(posedge i_rx_sclk or negedge i_rx_rst_n)
if (!i_rx_rst_n) begin
o_rx_left_chan <= 0;
o_rx_right_chan <= 0;
end else if (rx_lrclk_nedge) begin
o_rx_left_chan <= rx_left;
o_rx_right_chan <= {rx_right[AUDIO_DW-2:0], i_rx_sdata};
end
endmodule
i2s.v（网表）
module i2s_tx_AUDIO_DW16_DW01_inc_0 ( A, SUM );
input [15:0] A;
output [15:0] SUM;
wire [15:2] carry;
ah01d0 U1_1_14 ( .A(A[14]), .B(carry[14]), .CO(carry[15]), .S(SUM[14]) );
ah01d0 U1_1_13 ( .A(A[13]), .B(carry[13]), .CO(carry[14]), .S(SUM[13]) );
ah01d0 U1_1_12 ( .A(A[12]), .B(carry[12]), .CO(carry[13]), .S(SUM[12]) );
ah01d0 U1_1_11 ( .A(A[11]), .B(carry[11]), .CO(carry[12]), .S(SUM[11]) );
ah01d0 U1_1_10 ( .A(A[10]), .B(carry[10]), .CO(carry[11]), .S(SUM[10]) );
ah01d0 U1_1_9 ( .A(A[9]), .B(carry[9]), .CO(carry[10]), .S(SUM[9]) );
ah01d0 U1_1_8 ( .A(A[8]), .B(carry[8]), .CO(carry[9]), .S(SUM[8]) );
ah01d0 U1_1_7 ( .A(A[7]), .B(carry[7]), .CO(carry[8]), .S(SUM[7]) );
ah01d0 U1_1_6 ( .A(A[6]), .B(carry[6]), .CO(carry[7]), .S(SUM[6]) );
ah01d0 U1_1_5 ( .A(A[5]), .B(carry[5]), .CO(carry[6]), .S(SUM[5]) );
ah01d0 U1_1_4 ( .A(A[4]), .B(carry[4]), .CO(carry[5]), .S(SUM[4]) );
ah01d0 U1_1_3 ( .A(A[3]), .B(carry[3]), .CO(carry[4]), .S(SUM[3]) );
ah01d0 U1_1_2 ( .A(A[2]), .B(carry[2]), .CO(carry[3]), .S(SUM[2]) );
ah01d0 U1_1_1 ( .A(A[1]), .B(A[0]), .CO(carry[2]), .S(SUM[1]) );
inv0d1 U1 ( .I(A[0]), .ZN(SUM[0]) );
xr02d1 U2 ( .A1(carry[15]), .A2(A[15]), .Z(SUM[15]) );
endmodule
module i2s_tx_AUDIO_DW16 ( i_tx_sclk, i_tx_prescaler, i_tx_rst_n, o_tx_sclk,
o_tx_lrclk, o_tx_sdata, i_tx_left_chan, i_tx_right_chan );
input [15:0] i_tx_prescaler;
input [15:0] i_tx_left_chan;
input [15:0] i_tx_right_chan;
input i_tx_sclk, i_tx_rst_n;
output o_tx_sclk, o_tx_lrclk, o_tx_sdata;
wire i_tx_sclk, N16, N17, N18, N19, N20, N21, N22, N23, N24, N25, N26, N27,
N28, N29, N30, N31, N48, N49, N50, N51, N52, N53, N54, N55, N56, N57,
N58, N59, N60, N61, N62, N63, n18, n19, n21, n23, n1, n2, n3, n4, n5,
n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17, n24, n25, n26,
n27, n28, n29, n30, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40,
n41, n42, n43, n44, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54,
n55, n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68,
n69, n70, n71, n72, n73, n74, n75, n76, n77, n78, n79, n80;
wire [15:0] tx_bit_cnt;
wire [15:0] tx_right;
wire [15:0] tx_left;
assign o_tx_sclk = i_tx_sclk;
dfpfb1 \tx_bit_cnt_reg[0] ( .D(N16), .CPN(i_tx_sclk), .SDN(i_tx_rst_n),
.QN(n18) );
dfcfq1 \tx_bit_cnt_reg[1] ( .D(N17), .CPN(i_tx_sclk), .CDN(i_tx_rst_n), .Q(
tx_bit_cnt[1]) );
dfcfq1 \tx_bit_cnt_reg[2] ( .D(N18), .CPN(i_tx_sclk), .CDN(i_tx_rst_n), .Q(
tx_bit_cnt[2]) );
dfcfq1 \tx_bit_cnt_reg[3] ( .D(N19), .CPN(i_tx_sclk), .CDN(i_tx_rst_n), .Q(
tx_bit_cnt[3]) );
dfcfq1 \tx_bit_cnt_reg[4] ( .D(N20), .CPN(i_tx_sclk), .CDN(i_tx_rst_n), .Q(
tx_bit_cnt[4]) );
dfcfq1 \tx_bit_cnt_reg[5] ( .D(N21), .CPN(i_tx_sclk), .CDN(i_tx_rst_n), .Q(
tx_bit_cnt[5]) );
dfcfq1 \tx_bit_cnt_reg[6] ( .D(N22), .CPN(i_tx_sclk), .CDN(i_tx_rst_n), .Q(
tx_bit_cnt[6]) );
dfcfq1 \tx_bit_cnt_reg[7] ( .D(N23), .CPN(i_tx_sclk), .CDN(i_tx_rst_n), .Q(
tx_bit_cnt[7]) );
dfcfq1 \tx_bit_cnt_reg[8] ( .D(N24), .CPN(i_tx_sclk), .CDN(i_tx_rst_n), .Q(
tx_bit_cnt[8]) );
dfcfq1 \tx_bit_cnt_reg[9] ( .D(N25), .CPN(i_tx_sclk), .CDN(i_tx_rst_n), .Q(
tx_bit_cnt[9]) );
dfcfq1 \tx_bit_cnt_reg[10] ( .D(N26), .CPN(i_tx_sclk), .CDN(i_tx_rst_n),
.Q(tx_bit_cnt[10]) );
dfcfq1 \tx_bit_cnt_reg[11] ( .D(N27), .CPN(i_tx_sclk), .CDN(i_tx_rst_n),
.Q(tx_bit_cnt[11]) );
dfcfq1 \tx_bit_cnt_reg[12] ( .D(N28), .CPN(i_tx_sclk), .CDN(i_tx_rst_n),
.Q(tx_bit_cnt[12]) );
dfcfq1 \tx_bit_cnt_reg[13] ( .D(N29), .CPN(i_tx_sclk), .CDN(i_tx_rst_n),
.Q(tx_bit_cnt[13]) );
dfcfq1 \tx_bit_cnt_reg[14] ( .D(N30), .CPN(i_tx_sclk), .CDN(i_tx_rst_n),
.Q(tx_bit_cnt[14]) );
dfcfq1 \tx_bit_cnt_reg[15] ( .D(N31), .CPN(i_tx_sclk), .CDN(i_tx_rst_n),
.Q(tx_bit_cnt[15]) );
dfcfq1 o_tx_lrclk_reg ( .D(n23), .CPN(i_tx_sclk), .CDN(1'b1), .Q(o_tx_lrclk)
);
dfcfq1 o_tx_sdata_reg ( .D(n21), .CPN(i_tx_sclk), .CDN(1'b1), .Q(o_tx_sdata)
);
i2s_tx_AUDIO_DW16_DW01_inc_0 add_31_aco ( .A({N63, N62, N61, N60, N59, N58,
N57, N56, N55, N54, N53, N52, N51, N50, N49, N48}), .SUM({N31, N30,
N29, N28, N27, N26, N25, N24, N23, N22, N21, N20, N19, N18, N17, N16})
);
decfq1 \tx_right_reg[0] ( .D(i_tx_right_chan[0]), .ENN(n19), .CPN(i_tx_sclk), .CDN(i_tx_rst_n), .Q(tx_right[0]) );
decfq1 \tx_left_reg[15] ( .D(i_tx_left_chan[15]), .ENN(n19), .CPN(i_tx_sclk), .CDN(i_tx_rst_n), .Q(tx_left[15]) );
decfq1 \tx_left_reg[14] ( .D(i_tx_left_chan[14]), .ENN(n19), .CPN(i_tx_sclk), .CDN(i_tx_rst_n), .Q(tx_left[14]) );
decfq1 \tx_left_reg[13] ( .D(i_tx_left_chan[13]), .ENN(n19), .CPN(i_tx_sclk), .CDN(i_tx_rst_n), .Q(tx_left[13]) );
decfq1 \tx_left_reg[12] ( .D(i_tx_left_chan[12]), .ENN(n19), .CPN(i_tx_sclk), .CDN(i_tx_rst_n), .Q(tx_left[12]) );
decfq1 \tx_left_reg[11] ( .D(i_tx_left_chan[11]), .ENN(n19), .CPN(i_tx_sclk), .CDN(i_tx_rst_n), .Q(tx_left[11]) );
decfq1 \tx_left_reg[10] ( .D(i_tx_left_chan[10]), .ENN(n19), .CPN(i_tx_sclk), .CDN(i_tx_rst_n), .Q(tx_left[10]) );
decfq1 \tx_left_reg[9] ( .D(i_tx_left_chan[9]), .ENN(n19), .CPN(i_tx_sclk),
.CDN(i_tx_rst_n), .Q(tx_left[9]) );
decfq1 \tx_left_reg[8] ( .D(i_tx_left_chan[8]), .ENN(n19), .CPN(i_tx_sclk),
.CDN(i_tx_rst_n), .Q(tx_left[8]) );
decfq1 \tx_left_reg[7] ( .D(i_tx_left_chan[7]), .ENN(n19), .CPN(i_tx_sclk),
.CDN(i_tx_rst_n), .Q(tx_left[7]) );
decfq1 \tx_left_reg[6] ( .D(i_tx_left_chan[6]), .ENN(n19), .CPN(i_tx_sclk),
.CDN(i_tx_rst_n), .Q(tx_left[6]) );
decfq1 \tx_left_reg[5] ( .D(i_tx_left_chan[5]), .ENN(n19), .CPN(i_tx_sclk),
.CDN(i_tx_rst_n), .Q(tx_left[5]) );
decfq1 \tx_left_reg[4] ( .D(i_tx_left_chan[4]), .ENN(n19), .CPN(i_tx_sclk),
.CDN(i_tx_rst_n), .Q(tx_left[4]) );
decfq1 \tx_left_reg[3] ( .D(i_tx_left_chan[3]), .ENN(n19), .CPN(i_tx_sclk),
.CDN(i_tx_rst_n), .Q(tx_left[3]) );
decfq1 \tx_left_reg[2] ( .D(i_tx_left_chan[2]), .ENN(n19), .CPN(i_tx_sclk),
.CDN(i_tx_rst_n), .Q(tx_left[2]) );
decfq1 \tx_left_reg[1] ( .D(i_tx_left_chan[1]), .ENN(n19), .CPN(i_tx_sclk),
.CDN(i_tx_rst_n), .Q(tx_left[1]) );
decfq1 \tx_left_reg[0] ( .D(i_tx_left_chan[0]), .ENN(n19), .CPN(i_tx_sclk),
.CDN(i_tx_rst_n), .Q(tx_left[0]) );
decfq1 \tx_right_reg[15] ( .D(i_tx_right_chan[15]), .ENN(n19), .CPN(
i_tx_sclk), .CDN(i_tx_rst_n), .Q(tx_right[15]) );
decfq1 \tx_right_reg[14] ( .D(i_tx_right_chan[14]), .ENN(n19), .CPN(
i_tx_sclk), .CDN(i_tx_rst_n), .Q(tx_right[14]) );
decfq1 \tx_right_reg[13] ( .D(i_tx_right_chan[13]), .ENN(n19), .CPN(
i_tx_sclk), .CDN(i_tx_rst_n), .Q(tx_right[13]) );
decfq1 \tx_right_reg[12] ( .D(i_tx_right_chan[12]), .ENN(n19), .CPN(
i_tx_sclk), .CDN(i_tx_rst_n), .Q(tx_right[12]) );
decfq1 \tx_right_reg[11] ( .D(i_tx_right_chan[11]), .ENN(n19), .CPN(
i_tx_sclk), .CDN(i_tx_rst_n), .Q(tx_right[11]) );
decfq1 \tx_right_reg[10] ( .D(i_tx_right_chan[10]), .ENN(n19), .CPN(
i_tx_sclk), .CDN(i_tx_rst_n), .Q(tx_right[10]) );
decfq1 \tx_right_reg[9] ( .D(i_tx_right_chan[9]), .ENN(n19), .CPN(i_tx_sclk), .CDN(i_tx_rst_n), .Q(tx_right[9]) );
decfq1 \tx_right_reg[8] ( .D(i_tx_right_chan[8]), .ENN(n19), .CPN(i_tx_sclk), .CDN(i_tx_rst_n), .Q(tx_right[8]) );
decfq1 \tx_right_reg[7] ( .D(i_tx_right_chan[7]), .ENN(n19), .CPN(i_tx_sclk), .CDN(i_tx_rst_n), .Q(tx_right[7]) );
decfq1 \tx_right_reg[6] ( .D(i_tx_right_chan[6]), .ENN(n19), .CPN(i_tx_sclk), .CDN(i_tx_rst_n), .Q(tx_right[6]) );
decfq1 \tx_right_reg[5] ( .D(i_tx_right_chan[5]), .ENN(n19), .CPN(i_tx_sclk), .CDN(i_tx_rst_n), .Q(tx_right[5]) );
decfq1 \tx_right_reg[4] ( .D(i_tx_right_chan[4]), .ENN(n19), .CPN(i_tx_sclk), .CDN(i_tx_rst_n), .Q(tx_right[4]) );
decfq1 \tx_right_reg[3] ( .D(i_tx_right_chan[3]), .ENN(n19), .CPN(i_tx_sclk), .CDN(i_tx_rst_n), .Q(tx_right[3]) );
decfq1 \tx_right_reg[2] ( .D(i_tx_right_chan[2]), .ENN(n19), .CPN(i_tx_sclk), .CDN(i_tx_rst_n), .Q(tx_right[2]) );
decfq1 \tx_right_reg[1] ( .D(i_tx_right_chan[1]), .ENN(n19), .CPN(i_tx_sclk), .CDN(i_tx_rst_n), .Q(tx_right[1]) );
nd02d1 U3 ( .A1(o_tx_lrclk), .A2(n2), .ZN(n19) );
xr02d1 U4 ( .A1(o_tx_lrclk), .A2(n1), .Z(n23) );
an02d0 U5 ( .A1(n2), .A2(i_tx_rst_n), .Z(n1) );
mx02d0 U6 ( .I0(o_tx_sdata), .I1(n3), .S(i_tx_rst_n), .Z(n21) );
inv0d0 U7 ( .I(n4), .ZN(n3) );
mx08d1 U8 ( .I0(n5), .I1(n6), .I2(n7), .I3(n8), .I4(n9), .I5(n10), .I6(n11),
.I7(n12), .S0(o_tx_lrclk), .S1(n13), .S2(n18), .Z(n4) );
xn02d1 U9 ( .A1(n14), .A2(n15), .ZN(n13) );
nr02d0 U10 ( .A1(tx_bit_cnt[2]), .A2(n16), .ZN(n15) );
aoi2222d1 U11 ( .A1(tx_right[0]), .A2(n17), .B1(tx_right[4]), .B2(n24), .C1(
tx_right[2]), .C2(n25), .D1(tx_right[6]), .D2(n26), .ZN(n12) );
aoi2222d1 U12 ( .A1(tx_left[0]), .A2(n17), .B1(tx_left[4]), .B2(n24), .C1(
tx_left[2]), .C2(n25), .D1(tx_left[6]), .D2(n26), .ZN(n11) );
aoi2222d1 U13 ( .A1(tx_right[8]), .A2(n17), .B1(tx_right[12]), .B2(n24),
.C1(tx_right[10]), .C2(n25), .D1(tx_right[14]), .D2(n26), .ZN(n10) );
aoi2222d1 U14 ( .A1(tx_left[8]), .A2(n17), .B1(tx_left[12]), .B2(n24), .C1(
tx_left[10]), .C2(n25), .D1(tx_left[14]), .D2(n26), .ZN(n9) );
aoi2222d1 U15 ( .A1(tx_right[1]), .A2(n17), .B1(tx_right[5]), .B2(n24), .C1(
tx_right[3]), .C2(n25), .D1(tx_right[7]), .D2(n26), .ZN(n8) );
aoi2222d1 U16 ( .A1(tx_left[1]), .A2(n17), .B1(tx_left[5]), .B2(n24), .C1(
tx_left[3]), .C2(n25), .D1(tx_left[7]), .D2(n26), .ZN(n7) );
aoi2222d1 U17 ( .A1(tx_right[9]), .A2(n17), .B1(tx_right[13]), .B2(n24),
.C1(tx_right[11]), .C2(n25), .D1(tx_right[15]), .D2(n26), .ZN(n6) );
aoi2222d1 U18 ( .A1(tx_left[9]), .A2(n17), .B1(tx_left[13]), .B2(n24), .C1(
tx_left[11]), .C2(n25), .D1(tx_left[15]), .D2(n26), .ZN(n5) );
nr02d0 U21 ( .A1(n27), .A2(n28), .ZN(n26) );
nr02d0 U22 ( .A1(n27), .A2(n29), .ZN(n25) );
nr02d0 U23 ( .A1(n28), .A2(n30), .ZN(n24) );
nr02d0 U24 ( .A1(n29), .A2(n30), .ZN(n17) );
inv0d0 U25 ( .I(n27), .ZN(n30) );
xr02d1 U26 ( .A1(tx_bit_cnt[1]), .A2(n18), .Z(n27) );
inv0d0 U27 ( .I(n28), .ZN(n29) );
xn02d1 U28 ( .A1(n31), .A2(n32), .ZN(n28) );
an04d0 U29 ( .A1(n33), .A2(n34), .A3(n35), .A4(n36), .Z(n2) );
nr04d0 U30 ( .A1(n37), .A2(n38), .A3(n39), .A4(n40), .ZN(n36) );
nr04d0 U31 ( .A1(n41), .A2(n42), .A3(n43), .A4(n44), .ZN(n35) );
an04d0 U32 ( .A1(n45), .A2(n46), .A3(n47), .A4(n48), .Z(n34) );
ora211d1 U33 ( .C1(i_tx_prescaler[1]), .C2(n49), .A(n50), .B(n51), .Z(n33)
);
aoim22d1 U34 ( .A1(tx_bit_cnt[15]), .A2(n52), .B1(n18), .B2(
i_tx_prescaler[0]), .Z(n51) );
inv0d0 U35 ( .I(i_tx_prescaler[15]), .ZN(n52) );
an02d0 U36 ( .A1(tx_bit_cnt[15]), .A2(n53), .Z(N63) );
nr02d0 U37 ( .A1(n54), .A2(n48), .ZN(N62) );
an02d0 U38 ( .A1(tx_bit_cnt[13]), .A2(n53), .Z(N61) );
an02d0 U39 ( .A1(tx_bit_cnt[12]), .A2(n53), .Z(N60) );
nr02d0 U40 ( .A1(n55), .A2(n48), .ZN(N59) );
nr02d0 U41 ( .A1(n56), .A2(n48), .ZN(N58) );
an02d0 U42 ( .A1(tx_bit_cnt[9]), .A2(n53), .Z(N57) );
nr02d0 U43 ( .A1(n57), .A2(n48), .ZN(N56) );
nr02d0 U44 ( .A1(n58), .A2(n48), .ZN(N55) );
nr02d0 U45 ( .A1(n59), .A2(n48), .ZN(N54) );
an02d0 U46 ( .A1(tx_bit_cnt[5]), .A2(n53), .Z(N53) );
nr02d0 U47 ( .A1(n60), .A2(n48), .ZN(N52) );
nr02d0 U48 ( .A1(n14), .A2(n48), .ZN(N51) );
nr02d0 U49 ( .A1(n32), .A2(n48), .ZN(N50) );
nr02d0 U50 ( .A1(n49), .A2(n48), .ZN(N49) );
nr02d0 U51 ( .A1(n18), .A2(n48), .ZN(N48) );
inv0d0 U52 ( .I(n53), .ZN(n48) );
aoim22d1 U53 ( .A1(tx_bit_cnt[15]), .A2(n61), .B1(n62), .B2(
i_tx_prescaler[15]), .Z(n53) );
nd02d0 U54 ( .A1(i_tx_prescaler[15]), .A2(n62), .ZN(n61) );
aor22d1 U55 ( .A1(n50), .A2(n63), .B1(i_tx_prescaler[14]), .B2(n54), .Z(n62)
);
oai322d1 U56 ( .C1(n64), .C2(n44), .C3(n65), .A1(tx_bit_cnt[12]), .A2(n66),
.B1(tx_bit_cnt[13]), .B2(n67), .ZN(n63) );
inv0d0 U57 ( .I(n45), .ZN(n65) );
nd02d0 U58 ( .A1(tx_bit_cnt[12]), .A2(n66), .ZN(n45) );
inv0d0 U59 ( .I(i_tx_prescaler[12]), .ZN(n66) );
nr02d0 U60 ( .A1(n55), .A2(i_tx_prescaler[11]), .ZN(n44) );
aoi322d1 U61 ( .C1(n46), .C2(n68), .C3(n69), .A1(i_tx_prescaler[11]), .A2(
n55), .B1(i_tx_prescaler[10]), .B2(n56), .ZN(n64) );
inv0d0 U62 ( .I(tx_bit_cnt[11]), .ZN(n55) );
oai322d1 U63 ( .C1(n70), .C2(n42), .C3(n43), .A1(tx_bit_cnt[8]), .A2(n71),
.B1(tx_bit_cnt[9]), .B2(n72), .ZN(n69) );
inv0d0 U64 ( .I(i_tx_prescaler[8]), .ZN(n71) );
nr02d0 U65 ( .A1(n57), .A2(i_tx_prescaler[8]), .ZN(n43) );
inv0d0 U66 ( .I(tx_bit_cnt[8]), .ZN(n57) );
nr02d0 U67 ( .A1(n58), .A2(i_tx_prescaler[7]), .ZN(n42) );
aoi322d1 U68 ( .C1(n47), .C2(n73), .C3(n74), .A1(i_tx_prescaler[7]), .A2(n58), .B1(i_tx_prescaler[6]), .B2(n59), .ZN(n70) );
inv0d0 U69 ( .I(tx_bit_cnt[7]), .ZN(n58) );
oai322d1 U70 ( .C1(n75), .C2(n40), .C3(n41), .A1(tx_bit_cnt[4]), .A2(n76),
.B1(tx_bit_cnt[5]), .B2(n77), .ZN(n74) );
inv0d0 U71 ( .I(i_tx_prescaler[4]), .ZN(n76) );
nr02d0 U72 ( .A1(n60), .A2(i_tx_prescaler[4]), .ZN(n41) );
inv0d0 U73 ( .I(tx_bit_cnt[4]), .ZN(n60) );
nr02d0 U74 ( .A1(n14), .A2(i_tx_prescaler[3]), .ZN(n40) );
aoi322d1 U75 ( .C1(n78), .C2(n79), .C3(n80), .A1(i_tx_prescaler[3]), .A2(n14), .B1(i_tx_prescaler[2]), .B2(n32), .ZN(n75) );
inv0d0 U76 ( .I(tx_bit_cnt[3]), .ZN(n14) );
aor21d1 U77 ( .B1(n31), .B2(i_tx_prescaler[0]), .A(i_tx_prescaler[1]), .Z(
n80) );
inv0d0 U78 ( .I(n16), .ZN(n31) );
nd02d0 U79 ( .A1(n18), .A2(n49), .ZN(n16) );
inv0d0 U80 ( .I(n39), .ZN(n79) );
nr02d0 U81 ( .A1(n32), .A2(i_tx_prescaler[2]), .ZN(n39) );
inv0d0 U82 ( .I(tx_bit_cnt[2]), .ZN(n32) );
aor21d1 U83 ( .B1(n18), .B2(i_tx_prescaler[0]), .A(n49), .Z(n78) );
inv0d0 U84 ( .I(tx_bit_cnt[1]), .ZN(n49) );
inv0d0 U85 ( .I(n38), .ZN(n73) );
nr02d0 U86 ( .A1(n59), .A2(i_tx_prescaler[6]), .ZN(n38) );
inv0d0 U87 ( .I(tx_bit_cnt[6]), .ZN(n59) );
nd02d0 U88 ( .A1(tx_bit_cnt[5]), .A2(n77), .ZN(n47) );
inv0d0 U89 ( .I(i_tx_prescaler[5]), .ZN(n77) );
inv0d0 U90 ( .I(n37), .ZN(n68) );
nr02d0 U91 ( .A1(n56), .A2(i_tx_prescaler[10]), .ZN(n37) );
inv0d0 U92 ( .I(tx_bit_cnt[10]), .ZN(n56) );
nd02d0 U93 ( .A1(tx_bit_cnt[9]), .A2(n72), .ZN(n46) );
inv0d0 U94 ( .I(i_tx_prescaler[9]), .ZN(n72) );
aoim22d1 U95 ( .A1(tx_bit_cnt[13]), .A2(n67), .B1(n54), .B2(
i_tx_prescaler[14]), .Z(n50) );
inv0d0 U96 ( .I(tx_bit_cnt[14]), .ZN(n54) );
inv0d0 U97 ( .I(i_tx_prescaler[13]), .ZN(n67) );
endmodule
module i2s_rx_AUDIO_DW16 ( i_rx_sclk, i_rx_rst_n, i_rx_lrclk, i_rx_sdata,
o_rx_left_chan, o_rx_right_chan );
output [15:0] o_rx_left_chan;
output [15:0] o_rx_right_chan;
input i_rx_sclk, i_rx_rst_n, i_rx_lrclk, i_rx_sdata;
assign o_rx_left_chan[15] = 1'b0;
assign o_rx_left_chan[14] = 1'b0;
assign o_rx_left_chan[13] = 1'b0;
assign o_rx_left_chan[12] = 1'b0;
assign o_rx_left_chan[11] = 1'b0;
assign o_rx_left_chan[10] = 1'b0;
assign o_rx_left_chan[9] = 1'b0;
assign o_rx_left_chan[8] = 1'b0;
assign o_rx_left_chan[7] = 1'b0;
assign o_rx_left_chan[6] = 1'b0;
assign o_rx_left_chan[5] = 1'b0;
assign o_rx_left_chan[4] = 1'b0;
assign o_rx_left_chan[3] = 1'b0;
assign o_rx_left_chan[2] = 1'b0;
assign o_rx_left_chan[1] = 1'b0;
assign o_rx_left_chan[0] = 1'b0;
assign o_rx_right_chan[15] = 1'b0;
assign o_rx_right_chan[14] = 1'b0;
assign o_rx_right_chan[13] = 1'b0;
assign o_rx_right_chan[12] = 1'b0;
assign o_rx_right_chan[11] = 1'b0;
assign o_rx_right_chan[10] = 1'b0;
assign o_rx_right_chan[9] = 1'b0;
assign o_rx_right_chan[8] = 1'b0;
assign o_rx_right_chan[7] = 1'b0;
assign o_rx_right_chan[6] = 1'b0;
assign o_rx_right_chan[5] = 1'b0;
assign o_rx_right_chan[4] = 1'b0;
assign o_rx_right_chan[3] = 1'b0;
assign o_rx_right_chan[2] = 1'b0;
assign o_rx_right_chan[1] = 1'b0;
assign o_rx_right_chan[0] = 1'b0;
endmodule
module i2s_top ( i_tx_sclk, i_rst_n, i_tx_prescaler, i_tx_left_chan,
i_tx_right_chan, o_rx_left_chan, o_rx_right_chan );
input [15:0] i_tx_prescaler;
input [15:0] i_tx_left_chan;
input [15:0] i_tx_right_chan;
output [15:0] o_rx_left_chan;
output [15:0] o_rx_right_chan;
input i_tx_sclk, i_rst_n;
wire w_sclk, w_lrclk, w_sdata;
assign o_rx_left_chan[15] = 1'b0;
assign o_rx_left_chan[14] = 1'b0;
assign o_rx_left_chan[13] = 1'b0;
assign o_rx_left_chan[12] = 1'b0;
assign o_rx_left_chan[11] = 1'b0;
assign o_rx_left_chan[10] = 1'b0;
assign o_rx_left_chan[9] = 1'b0;
assign o_rx_left_chan[8] = 1'b0;
assign o_rx_left_chan[7] = 1'b0;
assign o_rx_left_chan[6] = 1'b0;
assign o_rx_left_chan[5] = 1'b0;
assign o_rx_left_chan[4] = 1'b0;
assign o_rx_left_chan[3] = 1'b0;
assign o_rx_left_chan[2] = 1'b0;
assign o_rx_left_chan[1] = 1'b0;
assign o_rx_left_chan[0] = 1'b0;
assign o_rx_right_chan[15] = 1'b0;
assign o_rx_right_chan[14] = 1'b0;
assign o_rx_right_chan[13] = 1'b0;
assign o_rx_right_chan[12] = 1'b0;
assign o_rx_right_chan[11] = 1'b0;
assign o_rx_right_chan[10] = 1'b0;
assign o_rx_right_chan[9] = 1'b0;
assign o_rx_right_chan[8] = 1'b0;
assign o_rx_right_chan[7] = 1'b0;
assign o_rx_right_chan[6] = 1'b0;
assign o_rx_right_chan[5] = 1'b0;
assign o_rx_right_chan[4] = 1'b0;
assign o_rx_right_chan[3] = 1'b0;
assign o_rx_right_chan[2] = 1'b0;
assign o_rx_right_chan[1] = 1'b0;
assign o_rx_right_chan[0] = 1'b0;
i2s_tx_AUDIO_DW16 i2s_tx ( .i_tx_sclk(i_tx_sclk), .i_tx_prescaler(
i_tx_prescaler), .i_tx_rst_n(i_rst_n), .o_tx_sclk(w_sclk),
.o_tx_lrclk(w_lrclk), .o_tx_sdata(w_sdata), .i_tx_left_chan(
i_tx_left_chan), .i_tx_right_chan(i_tx_right_chan) );
i2s_rx_AUDIO_DW16 i2s_rx ( .i_rx_sclk(w_sclk), .i_rx_rst_n(i_rst_n),
.i_rx_lrclk(w_lrclk), .i_rx_sdata(w_sdata) );
endmodule
tcl
remove_design -all
set power_preserve_rtl_hier_names "true"
set base_dir /data/trainee05/DC_2016.03/i2s/rtl
define_design_lib work -path "work"
set topname "i2s_top"
set link_library /data/trainee05/DC_2016.03/ref/libs/mw_lib/sc/LM/sc_max.db
set target_library /data/trainee05/DC_2016.03/ref/libs/mw_lib/sc/LM/sc_max.db
analyze -library WORK -format verilog /data/trainee05/DC_2016.03/i2s/rtl/i2s_top.v
analyze -library WORK -format verilog /data/trainee05/DC_2016.03/i2s/rtl/i2s_tx.v
analyze -library WORK -format verilog /data/trainee05/DC_2016.03/i2s/rtl/i2s_rx.v
elaborate $topname -lib work -update
current_design $topname
compile
write -format verilog -hierarchy -output /data/trainee05/DC_2016.03/i2s/i2s.v
#exit
直流误差
line# 30: Warning: /data/trainee05/DC_2016.03/i2s/rtl/i2s_rx.v:13: The construct 'declaration initial assignment' is not supported in synthesis; it is ignored. (VER-708)
line# 31: Warning: /data/trainee05/DC_2016.03/i2s/rtl/i2s_rx.v:14: The construct 'declaration initial assignment' is not supported in synthesis; it is ignored. (VER-708)
line# 33: Warning: /data/trainee05/DC_2016.03/i2s/rtl/i2s_rx.v:15: The construct 'declaration initial assignment' is not supported in synthesis; it is ignored. (VER-708)
line# 258: Warning: Verilog 'assign' or 'tran' statements are written out. (VO-4)