这就是我在pkg_test.vhd
中声明信号类型的方式:library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package pkg_test is type t_data_bus_array is array(natural range <>) of std_logic_vector; end pkg_test;
这是实体test_entity.vhd
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.pkg_test.all; entity test_entity is generic ( DATA_WIDTH : natural := 9; -- Data width of single input NUMBER_OF_INPUTS : natural := 4 -- Number of inputs ); port ( pi_data : in t_data_bus_array(NUMBER_OF_INPUTS-1 downto 0)(DATA_WIDTH-1 downto 0); po_data : out t_data_bus_array(NUMBER_OF_INPUTS-1 downto 0)(DATA_WIDTH-1 downto 0) ); end test_entity; architecture test_entity_behav of test_entity is begin po_data <= pi_data; end test_entity_behav;
这是我的错误。
[saka@serbia workspace]$ xrun -top test_entity -f filelist -elaborate -clean -sv -access +rwc -v200x xrun: 18.03-s001: (c) Copyright 1995-2018 Cadence Design Systems, Inc. xrun: *N,CLEAN: Removing existing directory ./xcelium.d. pkg_test.vhd: errors: 0, warnings: 0 test_entity.vhd: pi_data : in t_data_bus_array(NUMBER_OF_INPUTS-1 downto 0)(DATA_WIDTH-1 downto 0); | xmvhdl_p: *E,MISRPN (test_entity.vhd,42|73): expecting a right parenthesis (')') [1.1.1]. pi_data : in t_data_bus_array(NUMBER_OF_INPUTS-1 downto 0)(DATA_WIDTH-1 downto 0); | xmvhdl_p: *E,MISCOL (test_entity.vhd,42|84): expecting a colon (':') 87[4.3.3] 93[4.3.2]. pi_data : in t_data_bus_array(NUMBER_OF_INPUTS-1 downto 0)(DATA_WIDTH-1 downto 0); | xmvhdl_p: *E,EXPEND (test_entity.vhd,42|98): expecting the reserved word 'END' [1.1]. end test_entity; | xmvhdl_p: *E,EXPACE (test_entity.vhd,47|0): expecting a library unit [11.1]. architecture test_entity_behav of test_entity is | xmvhdl_p: *E,ENNOFN (test_entity.vhd,49|44): Intermediate file for entity 'TEST_ENTITY' could not be loaded, entity may require re-analysis. errors: 5, warnings: 0 xrun: *E,VHLERR: Error during parsing VHDL file (status 1), exiting.
很明显,我犯了一些错误
如果我使用此声明
type t_data_bus_array is array(natural range <>) of std_logic_vector(DATA_WIDTH-1 downto 0);
并且在这样的实体中
pi_data : in t_data_bus_array(NUMBER_OF_INPUTS-1 downto 0);
没有错误。
是否可以在vhdl中制作无约束数组的数组?我正在使用XCELIUM 18.03-s001。这就是我在pkg_test.vhd中声明信号类型的方式:库ieee;使用ieee.std_logic_1164.all;使用ieee ....
如果不使用VHDL2008,则不支持不受限制的std_logic_vector数组。