在Modelsim VHDL中编译

Question

我试图运行VHDL代码但是这个错误（vcom-11）不断出现。

vcom -work work -2002 -explicit -vopt -stats = none / nas / ei / home / ga94mel / Documents / VHDL _C / testbench.vhdl Model Technology ModelSim SE-64 vcom 10.4c Compiler 2015.07 Jul 19 2015

- 加载包STANDARD

- 加载包TEXTIO

- 正在加载包std_logic_1164

- 加载包NUMERIC_STD

- 编译实体MEM4096x12TEST

- 编译配置MEM4096x12TESTCONF

**错误：（vcom-11）找不到work.mem4096x12test（TB）。

**错误：/nas/ei/home/ga94mel/Documents/VHDL_C/test_bench.vhd(10）:( vcom-1537）块规范“TB”不是体系结构名称。

**错误：/nas/ei/home/ga94mel/Documents/VHDL_C/test_bench.vhd(11）：VHDL编译器退出

这是脚本：

    LIBRARY IEEE;
    USE IEEE.std_logic_1164.all;
    use IEEE.numeric_std.all;
    ENTITY MEM4096x12TEST IS
    end  MEM4096x12TEST ;

    --Configuration for Component Instantiation 

    configuration MEM4096x12TESTCONF of MEM4096x12TEST is
    for TB
     for UUT: MEM4096x12 use 
        entity WORK.RAM4096x12(behavioral)
         port map(
          w_en => w_en_C,
          addr => addr_C,
          data_in => data_in_C,
          data_out => data_out_C);
      end for;
    end for;
    end MEM4096x12TESTCONF; 

    architecture TB  of MEM4096x12TEST IS 
    Component MEM4096x12  
    PORT(
    w_en_C : in bit;
    addr_C : in bit_vector(11 downto 0);
    data_in_C: in bit_vector(11 downto 0);
    data_out_C: out  bit_vector (11 downto 0)
    );
    end Component ;
    Signal w_en_s :bit :='0';
    Signal addr_s, data_in_s, data_out_s  :  bit_vector(11 downto 0);
    begin 
    UUT: MEM4096x12 
    Port Map (w_en_C => w_en_s, 
        addr_C => addr_s,
        data_in_C => data_in_s , 
        data_out_C => data_out_s );
    w_en_s <= '1' after 5ns , '0' after 10 ns ; 
    data_in_s <="111111111111"  after 4 ns ; 
    addr_s <="000000000001"  after 4 ns , 
             "000000000010"  after 12 ns , 
             "000000000001"  after 20 ns ; 
    end TB ;

--Configuration for Entity Instantiation

configuration MEM4096x12TESTCONF of MEM4096x12TEST is
for TB
end For ; 
end MEM4096x12TESTCONF ;

architecture TB of MEM4096x12TEST_short IS 
Signal w_en_s :bit ; 
Signal addr_s,data_in_s , data_out_s  :  bit_vector(11 downto 0); 
begin 
UUT : entity Work.MEM4096x12(behavioral) 
port map ( w_en => w_en_s,
    addr => addr_s,
    data_in => data_in_s , 
    data_out => data_out_s); 
w_en_s <= '1' after 5ns , '0' after 10 ns ; 
data_in_s <= "111111111111"  after 4 ns ; 
addr_s <= "000000000001"  after 4 ns , 
          "000000000010"  after 12 ns , 
          "000000000001"  after 20 ns ; 
end TB ;

Answer 1

配置MEM4096x12TESTCONF需要遵循架构。