FIFO 缓冲区，Verilog，无法分配给未解析的线

Question

我正在为 fifo 缓冲区制作一个 verilog 代码。我写了测试台，但它不起作用，并给我带来了这些错误： full 无法分配给未解析的电线。 空无法分配给未解析的电线。 DATAOUT 无法分配给未解析的电线。

无论我怎样尝试都无法解决这些问题

fifo.v的代码：

module jFIFO(DATAOUT, full, empty, clock, reset, wn, rn, DATAIN);
  output reg [7:0] DATAOUT;
  output reg full, empty;
  input [7:0] DATAIN;
  input clock, reset, wn, rn;
  
  reg [2:0] state;
  reg [2:0] wptr, rptr;
  reg [7:0] memory [7:0];
  
  // FSM states
  localparam IDLE = 3'b000;
  localparam WRITE = 3'b001;
  localparam READ = 3'b010;
  
  always @(posedge clock) begin
    if (reset) begin
      memory[0] <= 0; memory[1] <= 0; memory[2] <= 0; memory[3] <= 0;
      memory[4] <= 0; memory[5] <= 0; memory[6] <= 0; memory[7] <= 0;
      DATAOUT <= 0; wptr <= 0; rptr <= 0; state <= IDLE;
      full <= 0; empty <= 1; // Initialize full and empty here
    end
    else begin
      case (state)
        IDLE: begin
          if (wn & !full)
            state <= WRITE;
          else if (rn & !empty)
            state <= READ;
        end
        
        WRITE: begin
          memory[wptr] <= DATAIN;
          wptr <= wptr + 1;
          state <= IDLE;
        end
        
        READ: begin
          DATAOUT <= memory[rptr];
          rptr <= rptr + 1;
          state <= IDLE;
        end
      endcase
      
      // Update full and empty based on state and wptr/rptr values
      full <= ((wptr == 3'b111) & (rptr == 3'b000)) ? 1 : 0;
      empty <= (wptr == rptr) ? 1 : 0;
    end
  end
endmodule

测试平台：

`timescale 1ns/1ps
module jFIFOTb;
  reg [7:0] DATAOUT;
  reg full, empty;
  reg clock, reset, wn, rn;
  reg [7:0] DATAIN;
  reg [2:0] state;

  jFIFO DUT(DATAOUT, full, empty, clock, reset, wn, rn, DATAIN);
initial begin 
clock = 0;
forever #1 clock = ~clock;
end 

initial begin 
$monitor ("[$t]\tstate = %b\tDATAIN = %b\tDATAOUT = %b\twn = %b\trn =%b\treset = %b",$time,state,DATAIN,DATAOUT,wn,rn,reset);
end
initial begin
    DATAIN = 8'd0;
    reset = 0;
   full = 1'b0;
   DATAOUT = 8'd0;
   empty = 1'b1;
    wn = 0; rn = 0;
state = 3'b000;
end

initial begin 
    // First write some data into the queue
    #5 wn = 1; rn = 0;
    #5 DATAIN = 8'd100;
    #5 DATAIN = 8'd150;
    #5 DATAIN = 8'd200;
    #5 DATAIN = 8'd40;
    #5 DATAIN = 8'd70;
    #5 DATAIN = 8'd65;
    #5 DATAIN = 8'd15;
    #5 DATAIN = 8'd55;
    // Now start reading and checking the values
    #5 wn = 0; rn = 1;
    #5 wn = 0; rn = 1;
    #5 wn = 0; rn = 1;
    #5 wn = 0; rn = 1;
    #5 wn = 0; rn = 1;
    #5 wn = 0; rn = 1;
    #5 wn = 0; rn = 1;
    #5 wn = 0; rn = 1;
    #5 $stop;
end
 
endmodule

Answer 1

DATAOUT，full 和empty 是jFIFO 模块的outputs。 您的测试台尝试在此处将值写入它们（创建多个驱动程序）：

initial begin
    DATAIN = 8'd0;
    reset = 0;
   full = 1'b0; <<<<<<<<<<
   DATAOUT = 8'd0; <<<<<<<<<
   empty = 1'b1; <<<<<<<
    wn = 0; rn = 0;
state = 3'b000;
end

没有意义。只需删除那些行。

Answer 2

发布的测试平台从不断言重置。

fifo状态机状态永远保持在x。

如果像@Serge 指出的那样重置 DUT 并删除多个驱动程序，那么模拟的行为更像是一个 fifo。

initial begin
    DATAIN = 8'd0;
    reset = 1;
    #4;
    reset = 0; 
    // full = 1'b0;
    // DATAOUT = 8'd0;
    // empty = 1'b1;
    wn = 0; rn = 0;
    state = 3'b000;
end

$monitor

声明有问题。这是一个修复：

initial  
$monitor ("time = %0t, DUT.state = %b DATAIN = %b, DATAOUT = %b, wn = %b, n =%b, reset = %b", $time, DUT.state, DATAIN, DATAOUT, wn, rn, reset
         );

我觉得RTL还有其他问题
出的数据和进的数据不匹配，空的flag看起来不对