同步寄存器设计VHDL

Question

我怎么做这个 register 设计同步？

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;

ENTITY register1 IS
  PORT (
    d_in : IN std_logic_vector(7 DOWNTO 0);
    load : IN std_logic;
    clear : IN std_logic;
    reg1 : INOUT std_logic_vector(7 DOWNTO 0)
  );
END register1;

ARCHITECTURE toplevel OF register1 IS
BEGIN
  PROCESS (load, clear)
  BEGIN
    IF clear = '1' THEN
      reg1 <= "00000000";
    ELSIF load = '1' THEN
      reg1 <= d_in;
    ELSIF load = '0' THEN
      reg1 <= reg1;
    END IF;
  END PROCESS;
END ARCHITECTURE toplevel;

Answer 1

为了实现同步设计，你需要添加一个你想同步的时钟，然后在上升沿执行你的逻辑，例如

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;

ENTITY register1 IS
  PORT (
    clk_i : IN std_logic;
    d_in : IN std_logic_vector(7 DOWNTO 0);
    load : IN std_logic;
    clear : IN std_logic;
    reg1 : INOUT std_logic_vector(7 DOWNTO 0)
  );
END register1;

ARCHITECTURE toplevel OF register1 IS
BEGIN
  PROCESS (clk_i, clear) -- Note the change of the sensitivity list
  BEGIN
    IF clear = '1' THEN
      reg1 <= "00000000";
    ELSIF rising_edge(clk_i) THEN
      IF load = '1' THEN
        reg1 <= d_in;
      ELSE
        reg1 <= reg1;
      END IF;
    END IF;
  END PROCESS;
END ARCHITECTURE toplevel;

请注意，这仍然是异步的 clear.Btw.为什么是 reg1 类型 INOUT?