在 verilog 代码中序列检测器中的预期时钟沿之前输出为高电平

Question

先生， 我为“1011”序列检测器编写了verilog代码。但在模拟中，当接收到“101”时输出为高电平。 IE。它在实际时钟沿之前的一个时钟周期为高电平。请帮我解决这个问题 // verilog 代码

module main(
input clk,
input rst,
input x,
output y
);
reg temp;
reg [1:0] present_state;
reg [1:0] next_state;
parameter [1:0] state_0 = 2'b00;
parameter [1:0] state_1 = 2'b01;
parameter [1:0] state_2 = 2'b10;
parameter [1:0] state_3 = 2'b11;


always @(posedge clk or posedge rst)
begin
if(rst)
present_state <= state_0;
else
present_state <= next_state;
end

always @(x or present_state)
begin
case(present_state)
state_0 : if( x )
begin
next_state  = state_1;
temp    = 1'b0;
end
else
begin
next_state  = state_0;
temp   = 1'b0;
end
state_1 : if( x )
begin
next_state  = state_1;
temp    = 1'b0;
end
else
begin
next_state  = state_2;
temp    = 1'b0;
end
state_2 : if( x )
begin
next_state  = state_3;
temp    = 1'b0;
end
else
begin
next_state  = state_0;  
temp    = 1'b0;   
end                                                   
state_3 : if( x )
begin
next_state  = state_1;
temp    = 1'b1;
end
else 
begin
next_state  = state_2;
temp   = 1'b0;
end
default  :     begin
next_state  = state_0;
temp    = 1'b0; 
end

endcase
end 
assign y = temp;
endmodule
//test bench
module tb_main(

);
reg clk;
reg rst;
reg x;
wire y;

main uut( clk,
rst,
x,
y
);
initial 
begin
clk = 1'b0;
rst = 1'b1;
x =1'b0;
#150 rst = 1'b0;
end

always
#50 clk <= ~clk;

initial
begin

#150 x = 1'b0;
#100 x = 1'b1;
#100 x = 1'b0;
#100 x = 1'b1;
#200 x = 1'b0;
#100 x = 1'b1;
#200 rst = 1'b1;
#200 $stop;
end
endmodule

我的模拟结果也附在这个问题上

Answer 1

测试台数据应该由时钟导出，就像同步设计的情况一样，所以至少将测试台更新为：

initial
begin
  #150; @(posedge clk) x = 1'b0;
  #100; @(posedge clk) x = 1'b1;
  #100; @(posedge clk) x = 1'b0;
  #100; @(posedge clk) x = 1'b1;
  #200; @(posedge clk) x = 1'b0;
  #100; @(posedge clk) x = 1'b1;
  #200; @(posedge clk) rst = 1'b1;
  #200; @(posedge clk) $stop;
end

希望这能帮助您继续前进，但您可能还会发现其他问题;-)

Answer 2

问题出在测试平台代码中。您有一个模拟竞争条件。

您需要以与设计中采样相同的方式从测试平台驱动同步输入 (

x

)：

• @(posedge clk)

• 非阻塞作业：

  <=

这是解决问题的测试台代码：

module tb_main;
   reg clk;
   reg rst;
   reg x;
   wire y;

main uut (
    clk,
    rst,
    x,
    y
);

initial begin
    clk = 0;
    rst = 1;
    x = 0;
    #150 rst = 0;
end

always #50 clk <= ~clk;

initial begin
    repeat (3) @(posedge clk); x <= 1;
    repeat (1) @(posedge clk); x <= 0;
    repeat (1) @(posedge clk); x <= 1;
    repeat (2) @(posedge clk); x <= 0;
    repeat (1) @(posedge clk); x <= 1;
    #200 rst = 1'b1;
    #200 $finish;
end
endmodule

显示正确输出时序的波形：