for循环VHDL中的If语句

Question

我想对8个输入和一个if语句进行for循环。我的目的是查找这8个端口中的最小端口。我知道这是什么错误，但是当（i）取值时我想使（Ι-1）之7。有什么想法吗？如果（a_unss（i）

LIBRARY ieee;
USE ieee.std_logic_1164 .all;
USe ieee.numeric_std .all;
---------------------------------------

ENTITY bitmin IS
generic
(     
size: integer            :=8

);
PORT
(
        A0,A1,A2,A3,A4,A5,A6,A7 : IN UNSIGNED (size-1 downto 0);

        MinOut:out  UNSIGNED (size-1 downto 0)
);     
END Entity;
-------------------------------------------------------------------------


ARCHITECTURE compare OF bitmin IS

type a_uns is array (0 to 7) of unsigned(7 downto 0);
signal a_unss:a_uns;



begin
        a_unss(0)<=(A0);
        a_unss(1)<=(A1);
        a_unss(2)<=(A2);
        a_unss(3)<=(A3);
        a_unss(4)<=(A4);
        a_unss(5)<=(A5);
        a_unss(6)<=(A6);
        a_unss(7)<=(A7);

process(a_unss) 


begin
MinOut<="00000000";
for i in 0 to 7 loop



              if (a_unss(i)<a_unss(i+1))and (a_unss(i)<a_unss(i+1)) and (a_unss(i)<a_unss(i+1)) and (a_unss(i)<a_unss(i+1))and (a_unss(i)<a_unss(i+1)) and (a_unss(i)<a_unss(i+1)) and (a_unss(i)<a_unss(i+1)) then
                     MinOut<=a_unss(i);


        end if;
    end loop;
end process;
END compare;

错误：

Error (10385): VHDL error at bitmin.vhd(48): index value 8 is outside the range (0 to 7) of object "a_unss"

Error (10658): VHDL Operator error at bitmin.vhd(48): failed to evaluate call to operator ""<""
Error (10658): VHDL Operator error at bitmin.vhd(48): failed to evaluate call to operator ""and""
Error (12153): Can't elaborate top-level user hierarchy
Error: Quartus Prime Analysis & Synthesis was unsuccessful. 4 errors, 1 warning
Error: Peak virtual memory: 4826 megabytes
Error: Processing ended: Thu Apr 09 19:39:04 2020
Error: Elapsed time: 0`enter code here`0:00:17
Error: Total CPU time (on all processors): 00:00:43

Answer 1

if (a_unss(i)<a_unss(i+1))and (a_unss(i)<a_unss(i+1)) and (a_unss(i)<a_unss(i+1)) and (a_unss(i)<a_unss(i+1))and (a_unss(i)<a_unss(i+1)) and (a_unss(i)<a_unss(i+1)) and (a_unss(i)<a_unss(i+1)) then

a_unss(i+1)的索引在您从0到7进行迭代时引起问题。i达到7时，i+1等于8，大于a_unss的边界。这就是消息：Error (10385): VHDL error at bitmin.vhd(48): index value 8 is outside the range (0 to 7) of object "a_unss"在说。

编辑

建议更新代码：

LIBRARY ieee;
USE ieee.std_logic_1164 .all;
USe ieee.numeric_std .all;
---------------------------------------

ENTITY bitmin IS
generic
(     
size: integer            :=8

);
PORT
(
        A0,A1,A2,A3,A4,A5,A6,A7 : IN UNSIGNED (size-1 downto 0);

        MinOut:out  UNSIGNED (size-1 downto 0)
);     
END Entity;
-------------------------------------------------------------------------


ARCHITECTURE compare OF bitmin IS

type a_uns is array (0 to 7) of unsigned(7 downto 0);
signal a_unss:a_uns;
signal MinOut_tmp : UNSIGNED (size-1 downto 0) := 0;
signal done_flag: STD_LOGIC := '0';


begin
        a_unss(0)<=(A0);
        a_unss(1)<=(A1);
        a_unss(2)<=(A2);
        a_unss(3)<=(A3);
        a_unss(4)<=(A4);
        a_unss(5)<=(A5);
        a_unss(6)<=(A6);
        a_unss(7)<=(A7);

process(a_unss) begin
    done_flag <= '0';

    for i in 0 to 7 loop
        if (a_unss(i) < MinOut_tmp) then
            MinOut_tmp<=a_unss(i);
        end if;
    end loop;

    done_flag <= '1';
end process;
END compare;


process(done_flag) begin
    if (done_flag == '1') then
        MinOut <= MinOut_tmp;
    end if;
end process;

Answer 2

正如其他人指出的那样，for循环索引超出了数组长度的范围。您还需要产生一个最小值链。

在下面的版本1中，使用了一条长链。

在下面的版本2中，使用了两个半长链，这使总传播延迟更短。

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity BitMin is
    generic
    (
        size: integer := 8

    );
    port
    (
        a0, a1, a2, a3, a4, a5, a6, a7: in unsigned(size - 1 downto 0);

        minout: out unsigned(size - 1 downto 0)
    );
end entity;

architecture Compare of BitMin is

    subtype TByte is unsigned(7 downto 0);

    type TByteArray is array(0 to 7) of TByte;

    signal inputs: TByteArray;
    signal min_chain: TByteArray;

    function Minimum(lhs, rhs: TByte) return TByte is
    begin
        if lhs < rhs then
            return lhs;
        end if;
        return rhs;
    end function;

begin
    inputs <= ( a0, a1, a2, a3, a4, a5, a6, a7 );

    -- Version 1 (one long chain)
    process(inputs, min_chain)
    begin
        min_chain(0) <= inputs(0);  -- Assume the first element in the array is the minimum.

        for i in 1 to 7 loop  -- Cycle through the remaining items to find the minimum.
            min_chain(i) <= Minimum(min_chain(i - 1), inputs(i));
        end loop;
        minout <= min_chain(7);
    end process;

    -- Version 2 (two half-length chains: 0..3 and 7..4)
    process(inputs, min_chain)
    begin
        min_chain(0) <= inputs(0);  -- Assume the first element in the array is the minimum.
        min_chain(7) <= inputs(7);  -- Assume the last element in the array is the minimum.

        for i in 1 to 3 loop  -- Cycle through the remaining items to find the minimum.
            min_chain(i) <= Minimum(min_chain(i - 1), inputs(i));  -- Work forwards from element 1.
            min_chain(7 - i) <= Minimum(min_chain(7 - i + 1), inputs(7 - i));  -- Work backwards from element 6.
        end loop;
        minout <= Minimum(min_chain(3), min_chain(4));  -- Find the minimum of the two chains.
    end process;

end Compare;

测试台

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity BitMin_TB is
end entity;

architecture V1 of BitMin_TB is

    constant size_tb: natural := 8;

    component BitMin is
        generic
        (
            size: integer := 8

        );
        port
        (
            a0, a1, a2, a3, a4, a5, a6, a7: in unsigned (size - 1 downto 0);

            minout: out unsigned (size - 1 downto 0)
        );
    end component;

    signal a0_tb, a1_tb, a2_tb, a3_tb, a4_tb, a5_tb, a6_tb, a7_tb: unsigned(size_tb - 1 downto 0);

    signal minout_tb: unsigned(size_tb - 1 downto 0);

begin

    DUT: BitMin
        generic map
        (
            size => size_tb

        )
        port map
        (
            a0 => a0_tb,
            a1 => a1_tb,
            a2 => a2_tb,
            a3 => a3_tb,
            a4 => a4_tb,
            a5 => a5_tb,
            a6 => a6_tb,
            a7 => a7_tb,

            minout => minout_tb
        );

    process
    begin
        wait for 10 ns;
        a0_tb <= "00000100";
        a1_tb <= "00001000";
        a2_tb <= "00010000";
        a3_tb <= "00100000";
        a4_tb <= "01000000";
        a5_tb <= "10000000";
        a6_tb <= "00000010";
        a7_tb <= "00000001";
        wait for 10 ns;
        --std.env.stop;
        wait;
    end process;

end architecture;

综合比较

两个版本都合成相同数量的逻辑元素，但是版本2更快。

版本1 RTL-一条长链

版本2 RTL-两个半长链