如何在系统 verilog 中随机化没有默认值的变量

问题描述 投票:0回答:1

我想要一个类,我想将所有 rand 变量放入一些默认值,只有当它们从句柄中分配非默认值时,才应该随机化

示例

typedef enum {
  NORTH = 0,
  SOUTH = 1,
  EAST  = 2,
  WEST  = 3,
  DEFAULT_DIR = 4
} direction_t;

class dir_class;
  
  rand direction_t dir;
  
 // I want something like
 // rand direction_t dir = DEFAULT_DIR;

  constraint dir_c
  { 
    if(dir == DEFAULT_DIR) 
    { 
      dir inside {NORTH,SOUTH,WEST,EAST};
    }
  }

endclass: dir_class

现在我想要的是,当我获取这个类的句柄时,我可能想分配一些非默认值(这可以通过内联约束来完成),但我不想使用它,因为我最终可能会拥有 100 个这样的变量.

所以我需要的是,最初所有变量都应该具有一些默认枚举值,例如

DEFAULT_RAND
,并且只有在它们保存此默认值时才进行随机化,否则保留通过句柄传递的值

constraints system-verilog uvm
1个回答
0
投票

这似乎有效

// Code your testbench here
// or browse Examples

typedef enum {
  NORTH = 0,
  SOUTH = 1,
  EAST  = 2,
  WEST  = 3,
  DEFAULT_DIR = 4
} direction_t;

class dir_class;
  
  rand direction_t dir;

  constraint dir_c
  { 
    if(dir == DEFAULT_DIR) 
    { 
      dir inside {NORTH,SOUTH,WEST,EAST};
    }
  }

      function new();

      endfunction
    
    
endclass: dir_class
    
class checker_class;
  
  rand dir_class direct;
  
  function new();
    direct = new();
  endfunction
  
  function void pre_randomzie();
    if(direct.dir != DEFAULT_DIR) begin
      direct.dir_c.constraint_mode(0);
    end
  endfunction 
  
endclass
  
    
module dir_module;
  
  checker_class check;
  
  initial begin
    check = new();
    check.direct.dir = DEFAULT_DIR;
    
    $display("DIR:%0s",check.direct.dir);
    
    check.randomize();
    
    $display("DIR:%0s",check.direct.dir);
    
    check.direct.dir = EAST;
    
    $display("DIR:%0s",check.direct.dir);
    
    check.randomize();
    
    $display("DIR:%0s",check.direct.dir);    
  end
  
  
endmodule: dir_module

输出

CPU time: .433 seconds to compile + .398 seconds to elab + .380 seconds to link
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  May  5 01:40 2024
DIR:DEFAULT_DIR
DIR:SOUTH
DIR:EAST
DIR:EAST
           V C S   S i m u l a t i o n   R e p o r t 
Time: 0 ns
CPU Time:      0.440 seconds;       Data structure size:   0.0Mb

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