使用VHDL模拟寄存器和增量器

Question

我设计了一个由寄存器和增量器组成的电路。每一个都应该为另一个提供输入，导致 PC 在时钟的每个上升沿递增 4。代码如下：

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity Register1 is
    port (
        CLK : in  STD_LOGIC;
        d   : in  STD_LOGIC_VECTOR(31 downto 0);
        q   : out STD_LOGIC_VECTOR(31 downto 0)
    );
end;

architecture Behavioral of Register1 is
begin
    process (CLK)
    begin
        if rising_edge(CLK) then
            q <= d;
        end if;
    end process;
end;


library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;


entity Incrementer is
    port (
        din  : in  STD_LOGIC_VECTOR(31 downto 0);
        dout : out STD_LOGIC_VECTOR(31 downto 0)
    );
end;

architecture DataFLow of Incrementer is
begin
    dout <= STD_LOGIC_VECTOR(UNSIGNED(din) + 4);
end;


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Test is
end Test;

architecture Struct of Test is

    component Register1 is
        port (
            CLK : in  STD_LOGIC;
            d   : in  STD_LOGIC_VECTOR(31 downto 0);
            q   : out STD_LOGIC_VECTOR(31 downto 0)
        );
    end component;

    component Incrementer is
        port (
            din  : in  STD_LOGIC_VECTOR(31 downto 0);
            dout : out STD_LOGIC_VECTOR(31 downto 0)
        );
    end component;
    
    signal CLK : STD_LOGIC := '0';
    signal PCN : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
    signal PC  : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');

    constant CLK_period: TIME := 10 ns;

begin
    -- The concurent clock signal
    CLK <= not CLK after CLK_period/2;

    PCreg:    Register1 port map (
                  CLK,
                  d => PCN,
                  q => PC
              );

    Incr1:    Incrementer port map (
                  din  => PC,
                  dout => PCN
              );

    -- The stimulus process
    verify: process
    begin
        wait for 80 ns;
    end process;
end;

然而，相关信号（PC、PCN）在我的模拟器（vivado）中显示为“X”。我做错了什么？

Answer 1

问题是，你没有初始化register1模块的信号q。因此，在仿真开始时，q 的值为“U”（未分配）。当您将 1 添加到“U”时，会得到“X”结果。所以你必须初始化q。这通常是通过同步或异步重置信号或带有初始化语句的信号定义来完成的，它将设计中的所有存储元素重置为不同于“U”的值。因此，使用异步重置信号，您的代码将如下所示：

process (RESET, CLK)
begin
    if RESET='1' then
        q <= (others => '0');
    elsif rising_edge(CLK) then
        q <= d;
    end if;
end process;