在 VHDl 中分配一堆 std_ulogic_vectors

Question

我有一个 Dram 信号和一个地址信号

 signal Address : std_ulogic_vector(31 downto 0);
 type memory_array is array (natural range <>) of std_ulogic_vector(31 downto 0);
 signal dram : memory_array(Address'range);

我要给dram的前5个元素赋值，剩下的应该为零

dram(0) <= std_ulogic_vector(to_unsigned(1, 32));
    dram(1) <= std_ulogic_vector(to_unsigned(2, 32));
    dram(2) <= std_ulogic_vector(to_unsigned(3, 32));
    dram(3) <= std_ulogic_vector(to_unsigned(4, 32));
    dram(4) <= std_ulogic_vector(to_unsigned(5, 32));
    dram(5 to 1023) <= (others => (others => '0'));

不，它给我一个语法错误“错误：[VRFC 10-4982] 'dram'附近的语法错误”（vivado 2022.1，VHDL 2008）在线

dram(0) <= std_ulogic_vector(to_unsigned(1, 32));

我不知道为什么，我需要帮助

我用它来模拟访问 RAm

library ieee;
use ieee.std_logic_1164.all;
use ieee.fixed_pkg.all;
use std.env.finish;
 
entity tb_Layer is
end tb_Layer;

architecture TEST of tb_Layer is

    component LSTM_Layer is
           
    Port (
        clk : in std_logic;
        rst : in std_logic;
        AddressLSTM : out std_ulogic_vector(31 downto 0)    
        Memory_in : out std_ulogic_vector(31 downto 0)      :
        Memory_out : in std_ulogic_vector(31 downto 0);
        WriteEn : out std_ulogic                            := '0';
        ReadEn : out std_ulogic                             := '0';
        InputFlag : in std_ulogic; 
        OutputFlag : out std_ulogic                         := '0'
    );
    
end component;
        signal clk : std_logic:='0';
        signal rst : std_logic;
        signal AddressLSTM : std_ulogic_vector(31 downto 0);
        signal Memory_in : std_ulogic_vector(31 downto 0) := (others => '1');
        signal Memory_out : std_ulogic_vector(31 downto 0);
        signal WriteEn : std_ulogic;
        signal ReadEn : std_ulogic;
        signal InputFlag : std_ulogic; 
        signal OutputFlag : std_ulogic := '1';
        type memory_array is array (natural range <>) of std_ulogic_vector(31 downto 0);
        signal dram : memory_array(AddressLSTM'range);
      

        dram(0) <= std_ulogic_vector(to_unsigned(1, 32));
    dram(1) <= std_ulogic_vector(to_unsigned(2, 32));
    dram(2) <= std_ulogic_vector(to_unsigned(3, 32));
    dram(3) <= std_ulogic_vector(to_unsigned(4, 32));
    dram(4) <= std_ulogic_vector(to_unsigned(5, 32));
    dram(5 to 1023) <= (others => (others => '0'));
             
BEGIN   
     
 uut: LSTM_Layer PORT MAP(

        clk => clk,
        rst=>rst,
        AddressLSTM => AddressLSTM,
        Memory_in => Memory_in,
        Memory_out => Memory_out,
        WriteEn => WriteEn,
        ReadEn => ReadEn,
        InputFlag => InputFlag,
        OutputFlag => OutputFlag
     ); 
     
    
    process (clk)
        begin
            if rising_edge(clk) then
                if WriteEn = '1' then
                    dram(to_integer(unsigned(AddressLSTM(31 downto 2)))) <= Memory_in ;
                elsif ReadEn = '1' then
                    Memory_out <= dram(to_integer(unsigned(AddressLSTM(31 downto 2))));
                end if;
            end if;
        end process;

    clock: process
        begin
                clk <= '0';
                rst<='0';
                wait for 100 ns;
                clk <= '1';
                wait for 100 ns; 
                clk <= '0';
                rst <= '1';
                wait for 100 ns;
                clk <= '1';
                wait for 100 ns; 
                clk <= not clk;
                wait for 100 ns;
                clk <= not clk;
                wait for 100 ns; 
                clk <= not clk;
  
        end process;
       
end TEST;