ShiftRegister Verilog HDL输出给出xxxxxxx

Question

我正在尝试在Verilog HDL中制作一个64位移位寄存器。当我在测试平台中尝试代码时，我只是得到xxxxxx作为输出，直到所有位都被移位为止。我不知道是什么问题。这是我的带有测试台和结果的代码：

module ShiftRegister (shift_out, clk, shift_in); //module ports
  parameter n = 64; //Parameter n declared to store 64
  input [n-1:0] shift_in; //64-bit input shift_in
  input clk; //Input clock
  output [n-1:0] shift_out; //64-bit output shift_out
  reg [n-1:0] ff; //64-bit flipflop
  assign shift_out = ff [n-1:0]; //give the output of the 64th bit
  //The operation of verilog: 
   always @ (posedge clk) //Always at the rising edge of the clock
   begin
     ff <= ff << 1;  //Shift bits to the left by 1
     ff[0] <= shift_in; //Take the input bits and give it to the first flipflop
     end
endmodule //ShiftRegister module

///Testbench\\\ 
module ShiftRegister_tb; //Module shiftRegister_tb
   parameter n = 64; //Parameter n declared to store 64
   reg [n-1:0] shift_in; //64-bit register input shift_in
   reg clk, rst; //register clock
   wire [n-1:0] shift_out; //64-bit wire output shift_out
   ShiftRegister DUT(shift_out, clk, shift_in); //Calling the module
  initial
    begin
    clk = 0; //clock = 0 initally
    shift_in = 64'd34645767785344; //Random decimal number to test the code 
    #100;
   end
 always #50 clk =~clk; //invert the clock input after 50ps
endmodule //ShiftRegister testbench

Answer 1

您将ff声明为reg，并且reg的默认值为x。在时钟的第一姿势之前，ff的所有64位均为x（未知）。在时钟的第一个姿势之后，ff[0]变为0，因为shift_in[0]为0。依此类推，直到达到64个时钟，然后所有ff位均为0。shift_out紧随ff。

通常，您的设计还会有一个重置信号。如果有一个，则可以在开始时断言复位，并在复位期间将ff分配为0。这是重置后的样子：

module ShiftRegister (shift_out, clk, shift_in, rst); //module ports
parameter n = 64; //Parameter n declared to store 64
input rst;
input [n-1:0] shift_in; //64-bit input shift_in
input clk; //Input clock
output [n-1:0] shift_out; //64-bit output shift_out
reg [n-1:0] ff; //64-bit flipflop
assign shift_out = ff [n-1:0]; //give the output of the 64th bit
//The operation of verilog: 
always @ (posedge clk or posedge rst) //Always at the rising edge of the clock
begin
if (rst) begin
    ff <= 0;
end else begin
    ff <= ff << 1;  //Shift bits to the left by 1
    ff[0] <= shift_in; //Take the input bits and give it to the first flipflop
end
end
endmodule


module ShiftRegister_tb; //Module shiftRegister_tb
parameter n = 64; //Parameter n declared to store 64
reg [n-1:0] shift_in; //64-bit register input shift_in
reg clk, rst; //register clock
wire [n-1:0] shift_out; //64-bit wire output shift_out
ShiftRegister DUT(shift_out, clk, shift_in,rst); //Calling the module
initial
begin
    clk = 0; //clock = 0 initally
    rst = 1;
    shift_in = 64'd34645767785344; //Random decimal number to test the code 
    #100;
    rst = 0;
    #50_000 $finish;
end
always #50 clk =~clk; //invert the clock input after 50ps
endmodule //ShiftRegister testbench