用VHDL中的向量进行并发信号分配

Question

我正在尝试使用GHDL编译此代码，我得到错误：'=>'是预期而不是'not'。我希望代码没有任何进程，也没有隐含的进程。

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

ENTITY decoder IS PORT 
    (c, b, a, g : IN std_logic;
    y : OUT std_logic_vector(7 DOWNTO 0));
END decoder;

ARCHITECTURE beh_decoder OF decoder IS
BEGIN
    y <= "10000000" WHEN (g NOT (a AND b AND c)) ELSE
         "01000000" WHEN ((a AND g) NOT (b AND c)) ELSE
         "00100000" WHEN ((b AND g) NOT (a AND c)) ELSE
         "00010000" WHEN ((a AND b AND g) NOT c) ELSE
         "00001000" WHEN ((c AND g) NOT (a AND b)) ELSE
         "00000100" WHEN ((a AND c AND g) NOT b) ELSE
         "00000010" WHEN ((b AND c AND g) NOT a) ELSE
         "00000001" WHEN ((a AND g) NOT (b AND c)) ELSE
         "00000000";
END ARCHITECTURE beh_decoder;

Answer 1

when表达式使用NOT门作为多输入门。

g NOT (a AND b AND c)

如果我们用Q =（a AND b AND c）代替你

g NOT Q

哪个没意义？很可能是GHDL抱怨的。

你想要的吗？

g OR NOT (a AND b AND c)

要么

g AND NOT (a AND b AND c)

根据您的评论，新代码可能如下所示。您需要确认逻辑，但它应该编译。

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

ENTITY decoder IS PORT 
    (c, b, a, g : IN std_logic;
    y : OUT std_logic_vector(7 DOWNTO 0));
END decoder;

ARCHITECTURE beh_decoder OF decoder IS
BEGIN
    y <= "10000000" WHEN (g AND NOT (a AND b AND c)) ELSE
         "01000000" WHEN ((a AND g) AND NOT (b AND c)) ELSE
         "00100000" WHEN ((b AND g) AND NOT (a AND c)) ELSE
         "00010000" WHEN ((a AND b AND g) AND NOT c) ELSE
         "00001000" WHEN ((c AND g) AND NOT (a AND b)) ELSE
         "00000100" WHEN ((a AND c AND g) AND NOT b) ELSE
         "00000010" WHEN ((b AND c AND g) AND NOT a) ELSE
         "00000001" WHEN ((a AND g) AND NOT (b AND c)) ELSE
         "00000000";
END ARCHITECTURE beh_decoder;