module IIR_filter(xn, clk, rst_n, yn);
input signed [3:0]xn;
input clk,rst_n;
output reg signed [3:0]yn;
reg signed [3:0]y_1,y_2,x_1,x_2,x_3;
always @(*)begin
yn = xn - (x_1) + (x_2) + (x_3)+ (y_1>>>1) + (y_2>>>2);
end
always @(posedge clk or negedge rst_n)
begin
if(rst_n == 0)
begin
y_1 <=0;y_2<=0;x_1<=0;x_2<=0;x_3<=0;
end
else
begin
y_1 <=yn; y_2<=y_1;
x_1<=xn; x_2<=x_1; x_3<=x_2;
end
end
endmodule
这是组合逻辑和时序逻辑的设计
// Code your testbench here
// or browse Examples
module IIR_filter_tb();
reg [3:0]xn;
reg clk,rst_n;
wire [3:0]yn;
integer i;
IIR_filter test(.xn(xn),
.clk(clk),
.rst_n(rst_n),
.yn(yn));
initial
begin
clk = 0;
#5 rst_n = 0;
xn = 4'b0000;
rst_n=1;
for(i = 0; i<4;i=i+1)
#20 xn = i;
$display("yn = %d", yn);
$finish;
end
always
begin
#10 clk = ~clk;
end
endmodule
这是测试台
问题是我不理解移位运算符的实现,并且递归结果被一一推送到下一个寄存器导致了问题。
我不在乎输出