为什么我在 modelsim 中看不到端口映射输入和输出?

问题描述 投票:0回答:1

所以我在网上找到了一个VHDL三角波教程只是为了检查,如何在modelsim中显示模拟波形,但它对我不起作用。

这张图显示了,他如何在 testbench/uut 下输出:wave

但对我来说,

wave_out
只出现在VHDL模块上,如果我将其设置为模拟,它只是一条平线。模块中的
Clk
reset
显示为未初始化。

这是代码,也是教程的链接:https://vhdlguru.blogspot.com/2015/04/triangle-wave-generator-in-vhdl.html

三角波VHDL代码:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity triangular is
port (clk : in std_logic; 
      wave_out : out std_logic_vector(7 downto 0);
      reset :in std_logic
     );
end triangular;

architecture Behavioral of triangular is

signal count,count2 : integer := 0;
signal direction : std_logic := '0';

begin

process(clk,reset)
begin
if(reset = '1') then
    count <= 0;
    count2 <= 129;
elsif(rising_edge(clk)) then
    --"direction" signal determines the direction of counting - up or down
    if(count = 253) then
        count <= 0;
        if(direction = '0') then
            direction <= '1';
            count2 <= 126;
        else
            direction <= '0';
            count2 <= 129;
        end if; 
    else
        count <= count + 1;
    end if;
    if(direction = '0') then
        if(count2 = 255) then
            count2 <= 0;
        else
            count2 <= count2 + 1; --up counts from 129 to 255 and then 0 to 127
        end if;
    else
        if(count2 = 255) then
            count2 <= 0;
        else
            count2 <= count2 - 1; --down counts from 126 to 0 and then 255 to 128
        end if;
    end if;
        
end if;
end process;

wave_out <= conv_std_logic_vector(count2,8);

end Behavioral;

测试台代码:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity tb_triangular is
end tb_triangular;

architecture Behavioral of tb_triangular is

component triangular is
port (clk : in std_logic; 
      wave_out : out std_logic_vector(7 downto 0);
      reset :in std_logic
     );
end component;

signal clk,reset : std_logic := '0';
signal wave_out : std_logic_vector(7 downto 0);

begin

uut : triangular port map(Clk,wave_out,reset);

Clk <= not Clk after 5 ns;

process
begin
reset <= '1';
wait for 100 ns;
reset <= '0';
wait;
end process;

end Behavioral;
vhdl modelsim
1个回答
0
投票

我在 Vivado 上运行您的设计和测试平台,结果如下:

Vivado simulation output

我没有看到一条平坦的线,而是看到一个奇怪的几乎是三角形的波形。

如果您在使用工具时遇到问题,请提供有关您正在使用的工具以及如何尝试将信号配置为模拟信号的更多信息。

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