所以我在网上找到了一个VHDL三角波教程只是为了检查,如何在modelsim中显示模拟波形,但它对我不起作用。
这张图显示了,他如何在 testbench/uut 下输出:
但对我来说,
wave_out
只出现在VHDL模块上,如果我将其设置为模拟,它只是一条平线。模块中的 Clk
和 reset
显示为未初始化。
这是代码,也是教程的链接:https://vhdlguru.blogspot.com/2015/04/triangle-wave-generator-in-vhdl.html
三角波VHDL代码:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity triangular is
port (clk : in std_logic;
wave_out : out std_logic_vector(7 downto 0);
reset :in std_logic
);
end triangular;
architecture Behavioral of triangular is
signal count,count2 : integer := 0;
signal direction : std_logic := '0';
begin
process(clk,reset)
begin
if(reset = '1') then
count <= 0;
count2 <= 129;
elsif(rising_edge(clk)) then
--"direction" signal determines the direction of counting - up or down
if(count = 253) then
count <= 0;
if(direction = '0') then
direction <= '1';
count2 <= 126;
else
direction <= '0';
count2 <= 129;
end if;
else
count <= count + 1;
end if;
if(direction = '0') then
if(count2 = 255) then
count2 <= 0;
else
count2 <= count2 + 1; --up counts from 129 to 255 and then 0 to 127
end if;
else
if(count2 = 255) then
count2 <= 0;
else
count2 <= count2 - 1; --down counts from 126 to 0 and then 255 to 128
end if;
end if;
end if;
end process;
wave_out <= conv_std_logic_vector(count2,8);
end Behavioral;
测试台代码:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity tb_triangular is
end tb_triangular;
architecture Behavioral of tb_triangular is
component triangular is
port (clk : in std_logic;
wave_out : out std_logic_vector(7 downto 0);
reset :in std_logic
);
end component;
signal clk,reset : std_logic := '0';
signal wave_out : std_logic_vector(7 downto 0);
begin
uut : triangular port map(Clk,wave_out,reset);
Clk <= not Clk after 5 ns;
process
begin
reset <= '1';
wait for 100 ns;
reset <= '0';
wait;
end process;
end Behavioral;