我有一个插件,超时和内部信号常数VHDL代码,例如,我想模拟计数器。我已经看过网络上的例子,我只看到的ModelSim监测的来龙去脉。不过,我也想看看内部信号,如计数器。我看见一个人只写模拟代码。我需要以下的一个简单的例子:具有一些来龙去脉和一些内部信号的代码。一个简单的通用TB代码,只需CLK增量或相似。我看到一个看起来正确的样本,但是当我适应我的代码,内部信号的ModelSim是不确定的。我可能失去了一些东西,但我的理解是,用Modelsim的一个重要特点是写一个通用的测试台的时钟,并用它来查看我的逻辑的直方图。当你的代码过程中,您将只需要根据需要结核病添加变量。如果有人在这两个原始和TB有代码的一些通用的代码或位置,他们将分享将是非常有益的。谢谢
我从来没有一个问题让ModelSim的绘制内部信号到波形。我只是将它从“对象”窗口拖放到信号的波形窗口。
下面是一个简单的例子。这是TestModule.vhd:
library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.ALL;
entity TestModule is
port (
ip_sl_ClkIn : in std_logic;
ip_slv_InputVal : in std_logic_vector(7 downto 0);
ip_sl_InputValid : in std_logic;
op_slv_OutputVal : out std_logic_vector(7 downto 0);
op_sl_OutputValid : out std_logic
);
end TestModule;
architecture Behavioral of TestModule is
--==========================
--== INTERNAL SIGNALS
--==========================
signal s_slv_InputNibbleSwap_1d : std_logic_vector(7 downto 0) := (others => 'X');
signal s_slv_Inverted_2d : std_logic_vector(7 downto 0) := (others => 'X');
signal s_sl_InputValid_1d : std_logic := '0';
signal s_sl_InputValid_2d : std_logic := '0';
begin
RegisterProc : process(ip_sl_ClkIn)
begin
if(rising_edge(ip_sl_ClkIn)) then
--Clock Cycle 1:
--=======================
--Take the input and swap nibble locations
s_slv_InputNibbleSwap_1d <= ip_slv_InputVal(3 downto 0) & ip_slv_InputVal(7 downto 4);
s_sl_InputValid_1d <= ip_sl_InputValid;
--Clock Cycle 2:
--=======================
--Invert the bits
s_slv_Inverted_2d <= not(s_slv_InputNibbleSwap_1d);
s_sl_InputValid_2d <= s_sl_InputValid_1d;
end if; --rising_edge(ip_sl_ClkIn)
end process RegisterProc;
--Route Outputs:
--=====================
op_slv_OutputVal <= s_slv_Inverted_2d;
op_sl_OutputValid <= s_sl_InputValid_2d;
end Behavioral;
下面是测试平台,TestModule_tb.vhd:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use std.textio.all;
ENTITY TestModule_tb IS
END TestModule_tb;
architecture behavior of TestModule_tb is
-- Component Declaration
-------------------------
component TestModule
Port (
ip_sl_ClkIn : in std_logic;
ip_slv_InputVal : in std_logic_vector ( 7 downto 0 );
ip_sl_InputValid : in std_logic;
op_slv_OutputVal : out std_logic_vector ( 7 downto 0 );
op_sl_OutputValid : out std_logic
);
end component;
--Signals Driven by Entity: TestModule
-------------------------
signal s_slv_OutputVal : std_logic_vector ( 7 downto 0 );
signal s_sl_OutputValid : std_logic;
--Test Stimulus Signals:
-------------------------
signal s_sl_ClkIn : std_logic;
signal s_slv_InputVal : std_logic_vector ( 7 downto 0 );
signal s_sl_InputValid : std_logic;
BEGIN
--Component Instantiation
uut : TestModule
Port Map (
ip_sl_ClkIn => s_sl_ClkIn , --in std_logic
ip_slv_InputVal => s_slv_InputVal , --in std_logic_vector ( 7 downto 0 )
ip_sl_InputValid => s_sl_InputValid , --in std_logic
op_slv_OutputVal => s_slv_OutputVal , --out std_logic_vector ( 7 downto 0 )
op_sl_OutputValid => s_sl_OutputValid --out std_logic
);
clkProc : process
begin
s_sl_ClkIn <= '1';
wait for 10 ns;
s_sl_ClkIn <= '0';
wait for 10 ns;
end process;
MainTestProcess : Process
Begin
s_slv_InputVal <= (others => '0');
s_sl_InputValid <= '0';
wait for 100 ns;
wait until rising_edge(s_sl_ClkIn); wait for 1 ps;
s_slv_InputVal <= X"AB";
s_sl_InputValid <= '1';
wait until rising_edge(s_sl_ClkIn); wait for 1 ps;
s_slv_InputVal <= X"FF";
s_sl_InputValid <= '0';
wait for 100 ns;
--Not a failure, but stops the simulation
assert false report "<---- NOT a failure. Testbench Complete" severity failure;
wait; -- Will wait forever
end process;
END;
这里是一个ModelSim的待办事项文件编制和模拟,TestModule_tb.do:
vlib work
vcom -reportprogress 300 -work work TestModule.vhd
vcom -reportprogress 300 -work work TestModule_tb.vhd
vsim -gui work.testmodule_tb
do TestModule_tb_wave.do
run -all
这里是ModelSim的波形DO文件,TestModule_tb_wave.do:
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /testmodule_tb/uut/ip_sl_ClkIn
add wave -noupdate /testmodule_tb/uut/ip_slv_InputVal
add wave -noupdate /testmodule_tb/uut/ip_sl_InputValid
add wave -noupdate /testmodule_tb/uut/op_slv_OutputVal
add wave -noupdate /testmodule_tb/uut/op_sl_OutputValid
add wave -noupdate /testmodule_tb/uut/s_slv_InputNibbleSwap_1d
add wave -noupdate /testmodule_tb/uut/s_slv_Inverted_2d
add wave -noupdate /testmodule_tb/uut/s_sl_InputValid_1d
add wave -noupdate /testmodule_tb/uut/s_sl_InputValid_2d
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {90738 ps} 0}
quietly wave cursor active 1
configure wave -namecolwidth 331
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {0 ps} {231001 ps}