我正在尝试编写控制 4 位计数器（LED）的 Verilog HDL 程序。按“key0”递增计数器，按“key1”递减计数器。按键具有反转逻辑，因此活动状态较低。默认情况下，按键上拉至 VCC3P3。我正在尝试编写一个没有时钟信号的程序。
我的FPGA是Altera MAX10 10M50DAF484C7G。
我的程序不正确：
module button_4bit_counter(
input key0,
input key1,
output [3:0] ledr
);
reg [3:0] counter = 0;
always @(negedge key0 or negedge key1)
begin
if (!key0)
counter <= counter + 1;
else if (!key1)
counter <= counter - 1;
end
assign ledr = counter;
endmodule
将此程序加载到 FPGA 后，所有 LED 都会亮起。递减 key1 效果很好，但按下 key0 会随机改变 LED 状态。我还在按键的引脚上设置了施密特触发器。
有一个警告列表：
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Warning (10230): Verilog HDL assignment warning at button_4bit_counter.v(12): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at button_4bit_counter.v(14): truncated value with size 32 to match size of target (4)
Warning (13004): Presettable and clearable registers converted to equivalent circuits with latches. Registers power-up to an undefined state, and DEVCLRn places the registers in an undefined state.
Warning (13310): Register "counter[0]" is converted into an equivalent circuit using register "counter[0]~_emulated" and latch "counter[0]~1"
Warning (13310): Register "counter[1]" is converted into an equivalent circuit using register "counter[1]~_emulated" and latch "counter[1]~5"
Warning (13310): Register "counter[2]" is converted into an equivalent circuit using register "counter[2]~_emulated" and latch "counter[2]~9"
Warning (13310): Register "counter[3]" is converted into an equivalent circuit using register "counter[3]~_emulated" and latch "counter[3]~13"
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Warning (335093): The Timing Analyzer is analyzing 4 combinational loops as latches. For more details, run the Check Timing command in the Timing Analyzer or view the "User-Specified and Inferred Latches" table in the Analysis & Synthesis report.
Critical Warning (332012): Synopsys Design Constraints File file not found: 'button_4bit_counter.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Warning (332125): Found combinational loop of 4 nodes
Warning (332126): Node "Add0~1|combout"
Warning (332126): Node "counter[3]~14|datad"
Warning (332126): Node "counter[3]~14|combout"
Warning (332126): Node "Add0~1|dataa"
Warning (332125): Found combinational loop of 4 nodes
Warning (332126): Node "Add0~0|combout"
Warning (332126): Node "counter[2]~10|datad"
Warning (332126): Node "counter[2]~10|combout"
Warning (332126): Node "Add0~0|datab"
Warning (332125): Found combinational loop of 4 nodes
Warning (332126): Node "Add1~0|combout"
Warning (332126): Node "counter[1]~6|datad"
Warning (332126): Node "counter[1]~6|combout"
Warning (332126): Node "Add1~0|datad"
Warning (332125): Found combinational loop of 2 nodes
Warning (332126): Node "counter[0]~2|combout"
Warning (332126): Node "counter[0]~2|datad"
Warning (169177): 2 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing MAX 10 Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
Info (169178): Pin key0 uses I/O standard 2.5 V Schmitt Trigger at B8
Info (169178): Pin key1 uses I/O standard 2.5 V Schmitt Trigger at A7
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Warning (335093): The Timing Analyzer is analyzing 4 combinational loops as latches. For more details, run the Check Timing command in the Timing Analyzer or view the "User-Specified and Inferred Latches" table in the Analysis & Synthesis report.
Critical Warning (332012): Synopsys Design Constraints File file not found: 'button_4bit_counter.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Warning (332125): Found combinational loop of 4 nodes
Warning (332126): Node "Add0~1|combout"
Warning (332126): Node "counter[3]~14|datad"
Warning (332126): Node "counter[3]~14|combout"
Warning (332126): Node "Add0~1|datab"
Warning (332125): Found combinational loop of 4 nodes
Warning (332126): Node "Add0~0|combout"
Warning (332126): Node "counter[2]~10|datad"
Warning (332126): Node "counter[2]~10|combout"
Warning (332126): Node "Add0~0|datac"
Warning (332125): Found combinational loop of 4 nodes
Warning (332126): Node "Add1~0|combout"
Warning (332126): Node "counter[1]~6|datab"
Warning (332126): Node "counter[1]~6|combout"
Warning (332126): Node "Add1~0|datad"
Warning (332125): Found combinational loop of 2 nodes
Warning (332126): Node "counter[0]~2|combout"
Warning (332126): Node "counter[0]~2|datab"
Critical Warning (332148): Timing requirements not met
Critical Warning (332148): Timing requirements not met
Critical Warning (332148): Timing requirements not met