尽管相等，但断言失败

Question

我在断言中遇到了奇怪的失败。如错误消息所示，尽管相等为真，但它失败。我正在简单计算u2模块的4个输入的总和，并确认该总和等于两个输出的总和。

property CSA_add;
    @(posedge clk) disable iff(reset) (u2.VS + u2.VC)&'hFFFF == (u2.VS_x + u2.VS_y + u2.VC_x + u2.VC_y)&'hFFFF;
endproperty 

assert property (CSA_add)
       error <= 1'b0; 
    else begin
       $warning("%x result != %x  cheat\n",(u2.VS_x + u2.VS_y + u2.VC_x + u2.VC_y)&'hFFFF
                                       ,(u2.VS + u2.VC)&'hFFFF );
       error <= 1'b1;
    end

我收到这些错误消息：

** Warning: 0000049d result != 0000049d  cheat
Time: 3 ns Started: 3 ns  Scope: tb_shift File: C::....../tb_shift.sv Line: 29<br>
** Warning: 00000163 result != 00000163  cheat
Time: 5 ns Started: 5 ns  Scope: tb_shift File: C::....../tb_shift.sv Line: 29<br>
** Warning: 000000a4 result != 000000a4  cheat
Time: 7 ns Started: 7 ns  Scope: tb_shift File: C::....../tb_shift.sv Line: 29<br>
** Warning: 000006b3 result != 000006b3  cheat
Time: 9 ns Started: 9 ns  Scope: tb_shift File: C:....../tb_shift.sv Line: 29<br>
** Warning: 00000580 result != 00000580  cheat
Time: 11 ns Started: 11 ns  Scope: tb_shift File: C:/Users/John/Dropbox/University/3rd_year/ELEC3017/tb_shift.sv Line: 29

Answer 1

[当显示的消息与校验码之间存在差异时，通常是竞争状况的结果。在这种情况下，被比较的信号与采样时钟同时改变。

一种补救方法是更改​​断言的采样点。例如，更改

@(posedge clk) 

至：

@(negedge clk)