vivado中的picorv32 risc-v实现,2018.2

问题描述 投票:0回答:1

这是核心:https://github.com/cliffordwolf/picorv32

我在vivado中实现核心时遇到问题。我已经安装了riscv gnu工具链,并且我确定它可以正常工作,我修改了Makefile($ TOOLCHAINPREFIX)。

[我运行了makfile的make firmware.hex(来自scripts / vivado文件夹),然后我运行了make synth_system命令在vivado中运行synth_system.tcl,并为我的fpga生成了比特流。

我的fpga是一个arty a7-35t开发板,我修改了synth_system.xdc约束文件以匹配arty a7引脚而不是basys 3(默认情况下是这样)。我还在.tcl脚本中更改了板的名称。我还修改了firmware.c,使其仅在地址0x10000000上输出零和一个,并且在它们之间稍有延迟,以使电路板的LED闪烁。

但是,de LED指示灯不闪烁,唯一的效果是,当我按下复位按钮时,陷阱信号打开(我将复位置于FPGA的button0上,并将陷阱信号置于绿色的led 0上。) >

所以,无论我做什么,唯一的结果就是,当我按下复位键时,我的绿色LED亮了,仅此而已。

我可能缺少一些东西...

[请帮助我,我不知道该怎么办!

提前谢谢您!

P.S。我要从scripts / vivado文件夹附加修改后的文件。

////////////////////////
firmware.c
///////////////////
void putc(int c)
{
(volatile int)0x10000000 = c;
}

void puts(const char *s)
{
while (*s) putc(*s++);
}

void *memcpy(void dest, const void src, int n)
{
while (n) {
n--;
((char)dest)[n] = ((char)src)[n];
}
return dest;
}

int message1=0xFFFFFFFF;
int message2=0x00000000;
int flag=1;

void main()
{

while(1)
{ 
    if(flag)
    {
        //putc(message2);
        *(volatile int*)0x10000000 = message2;
        flag=0;
    }
    else
    {   
        *(volatile int*)0x10000000 = message1;
        //putc(message1);
        flag=1;

    }

    for (long int i = 0; i=500000; i++);

}
}
////////////////////////////////////
synth_system.tcl
///////////////////////////////////

read_verilog system.v
read_verilog ../../picorv32.v
read_xdc synth_system.xdc

synth_design -part xc7a35ti-csg324-1L -top system
opt_design
place_design
route_design

report_utilization
report_timing

write_verilog -force synth_system.v
write_bitstream -force synth_system.bit
//////////////////////////////////////////////
synth_system.xdc
/////////////////////////////////////

XDC File for Arty A7 Board
###########################

set_property PACKAGE_PIN E3 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
create_clock -period 10.00 [get_ports clk]

Blue from RGB LEDS and also regular LEDS from Arty A7
set_property PACKAGE_PIN E1 [get_ports {out_byte[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[0]}]
set_property PACKAGE_PIN G4 [get_ports {out_byte[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[1]}]
set_property PACKAGE_PIN H4 [get_ports {out_byte[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[2]}]
set_property PACKAGE_PIN K2 [get_ports {out_byte[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[3]}]
set_property PACKAGE_PIN H5 [get_ports {out_byte[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[4]}]
set_property PACKAGE_PIN J5 [get_ports {out_byte[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[5]}]
set_property PACKAGE_PIN T9 [get_ports {out_byte[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[6]}]
set_property PACKAGE_PIN T10 [get_ports {out_byte[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[7]}]

first is buton 0 trap and out_byte_en is on green LEDS from the RGB leds
set_property PACKAGE_PIN D9 [get_ports {resetn}]
set_property IOSTANDARD LVCMOS33 [get_ports {resetn}]
set_property PACKAGE_PIN F6 [get_ports {trap}]
set_property IOSTANDARD LVCMOS33 [get_ports {trap}]
set_property PACKAGE_PIN J4 [get_ports {out_byte_en}]
set_property IOSTANDARD LVCMOS33 [get_ports {out_byte_en}]

set_property CONFIG_VOLTAGE 3.3 [current_design]
#where value2 is the voltage provided to configuration bank 0

set_property CFGBVS VCCO [current_design]
#where value1 is either VCCO or GND

//////////////////////////////////////////////////////////////////

I also modified the code for system.v to see if the project works at all.
end else begin
//////////////////
last part of system.v
//////////////////////
always @(posedge clk) begin
m_read_en <= 0;
mem_ready <= mem_valid && !mem_ready && m_read_en;

        m_read_data <= memory[mem_addr >> 2];
        mem_rdata <= m_read_data;

        out_byte_en <= 0;
                    out_byte<=8'h0F;  ////MODIFIED PART
        (* parallel_case *)
        case (1)
            mem_valid && !mem_ready && !mem_wstrb && (mem_addr >> 2) < MEM_SIZE: begin
                m_read_en <= 1;
            end
            mem_valid && !mem_ready && |mem_wstrb && (mem_addr >> 2) < MEM_SIZE: begin
                if (mem_wstrb[0]) memory[mem_addr >> 2][ 7: 0] <= mem_wdata[ 7: 0];
                if (mem_wstrb[1]) memory[mem_addr >> 2][15: 8] <= mem_wdata[15: 8];
                if (mem_wstrb[2]) memory[mem_addr >> 2][23:16] <= mem_wdata[23:16];
                if (mem_wstrb[3]) memory[mem_addr >> 2][31:24] <= mem_wdata[31:24];
                mem_ready <= 1;
            end
            mem_valid && !mem_ready && |mem_wstrb && mem_addr == 32'h1000_0000: begin
                out_byte_en <= 1;
                out_byte <= 8'h01;  ///////////MODIFIED PART
                mem_ready <= 1;
            end
        endcase
    end
end endgenerate
endmodule

[我也试图只通过while(1)在它们上写入0xFF来点亮LED,但这也不起作用:

void putc(int c)
{
    *(volatile int*)0x10000000 = c;
}

void puts(const char *s)
{
    while (*s) putc(*s++);
}

void *memcpy(void *dest, const void *src, int n)
{
    while (n) {
        n--;
        ((char*)dest)[n] = ((char*)src)[n];
    }
    return dest;
}

int message1=0xFFFFFFFF;
int message2=0x00000000;
int flag=1;

void main()
{
    while(1)
    {
    *(volatile int*)0x10000000 = message1;
    }

}

结论:即使.C程序以地址0x1000_0000进行写入,输出字节的蓝色led仅以模式0x0F点亮(二进制为00001111,因此仅后者8点亮)一定有问题,我似乎找不到答案。

这是核心:https://github.com/cliffordwolf/picorv32我在vivado中实现核心时遇到问题。我已经安装了riscv gnu工具链,并且我确定它可以正常工作,我修改了...

c++ c verilog hdl vivado
1个回答
0
投票

[如果您尝试使用64位编译器(大多数发行版提供)为32位RISC-V rv32i内核构建代码,那么您需要添加-mabi=ilp32 -march=rv32i以使其进入rv32i模式。

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