将 001 B 处的值读取为 000 处的第一个值，实际上是 A？

Question

这是 ram 的 System Verilog 设计代码，我需要在其中写入数据。

always @(posedge clk or posedge rst) begin
  if (rst) begin
    // Reset condition
    addr_r <= 8'b0;
  end else begin
    // WRITE to RAM
    if (we) begin
      ram[addr_r] <= data_in;
    end

    // READ from RAM
    addr_r <= address_ram;
  end
end

这里是将值写入 RAM 的测试平台代码。我想比较 RAM 和 ROM 中的值（参考字符串）。但这些值是以不同的顺序写入的。

 // Initial Block
  initial begin
    clk = 0;
    rst = 1; // Assert reset initially
    we = 0;
    data_in = 8'b0;
    address_rom = 3'b0;
    address_ram = 3'b0;
    // Apply reset for some time
    #10 rst = 0;
    #10;
    // Write data to RAM
    we = 1;
    address_ram = 3'b000;
    data_in = 8'b01000001; // 'A'
    #10;

    we = 1;
    address_ram = 3'b001;
    data_in = 8'b01000010; // 'B'
    #10;

    we = 1;
    address_ram = 3'b010;
    data_in = 8'b01000011; // 'C'
    #10;
    we = 1;
    address_ram = 3'b111;
    data_in = 8'b01001000; // 'H'
    #10;
    we = 0;
    #10;
    address_ram = 3'b000;    
    // Read data iteratively
   // Read data iteratively
repeat (2**3) begin
  #10;
  $display("Read Data from ROM at address %b: %c", address_rom, data_rom_out);
  $display("Read Data from RAM at address %b: %c", address_ram, q_ram_out);
  // Increment addresses after displaying values
  address_rom = address_rom + 1;
  address_ram = address_ram + 1;
end
    // Add more stimulus as needed
    #200 $finish;
end

我尝试更改时间参数，即 #10 到 20 30 等尝试来回移动它，但输出仍然始终错误

Read Data from ROM at address 000: A
Read Data from RAM at address 000: B
Read Data from ROM at address 001: B
Read Data from RAM at address 001: C
Read Data from ROM at address 010: C
Read Data from ROM at address 111: H
Read Data from RAM at address 111: 

这是正在读取的输出数据 但是，如果我删除除 000 写入 A 之外的所有数据写入行...它会选取正确的值作为 000 RAM 值作为 A 但如果我写下所有值，它会将 000 显示为 B

Answer 1

我尝试在这里回答类似的问题：我得到的输出是错误的

问题是您使用注册的

ram_address

即

addr_r

进行书写，但使用未注册的

we

和

data_in

。在那里检查我的答案。在该答案中，我假设为

negedge rst

，您可以将其更改为

posedge rst

。