在生成块内使用模块时加载设计错误

Question

我在单独的文件中有以下模块。当我尝试运行我的

RC_ADD_SUB_32

模块时，出现错误

“inst”实例化失败。地区： /RC_ADD_SUB_32_TB/obj/rc_gen_loop[0]/FULL_ADDER 设计单元为 未找到。加载设计时出错。

实例化全加器在

generate

块内不起作用。我在

rc_add_sub_32.v

文件中实例化全加器时遇到问题。有什么想法吗？

full_adder.v

module FULL_ADDER(S,CO,A,B, CI);
    output S,CO;
    input A,B, CI;

    wire HF_1_Y, HF_1_C, HF_2_C; //Half Adder 1 Y, Half Adder 1 C and Half Adder 2 C

    HALF_ADDER inst_01 (.A(A), .B(B), .Y(HF_1_Y), .C(HF_1_C));
    HALF_ADDER inst_02 (.A(HF_1_Y), .B(CI), .Y(S), .C(HF_2_C));
    or inst_03(CO, HF_2_C, HF_1_C);
endmodule;

rc_add_sub_32.v

module RC_ADD_SUB_32(Y, CO, A, B, SnA);
    // output list
    //output [63:0] Y;
    output [`DATA_INDEX_LIMIT:0] Y; //Our result
    output CO; 
    // input list
    //input [63:0] A;
    //input [63:0] B;
    input [`DATA_INDEX_LIMIT:0] A;
    input [`DATA_INDEX_LIMIT:0] B;

    input SnA;

    //full adder -> full adder connection
    wire [`DATA_INDEX_LIMIT:0] CO_TO_CI;
    wire [`DATA_INDEX_LIMIT:0] XOR_OUT;

    genvar i;
    generate
        for(i=0; i<32; i=i+1)
        begin: rc_gen_loop
        /*
            Cases:
            Index 0: CI is SnA  CO -> CI[1]
            Index 31: CI is CO from index 30, CO is output CO,
            Index 1-30: CI is from previous CO, CO points to next CI
        */ 
            xor xors(XOR_OUT[i], SnA, B[i]);
            if(i==0) 
            begin: 
                FULL_ADDER inst(.S(Y[i]), .CO(CO_TO_CI[i]), .A(A[i]), .B(XOR_OUT[i]), .CI(SnA));
            end
            else if(i==31) 
            begin:
                FULL_ADDER inst(.S(Y[i]), .CO(CO), .A(A[i]), .B(XOR_OUT[i]), .CI(CO_TO_CI[i-1]));
            end
            else if(i!=31 && i!=0) 
            begin:
                FULL_ADDER inst(.S(Y[i]), .CO(CO_TO_CI[i]), .A(A[i]), .B(XOR_OUT[i]), .CI(CO_TO_CI[i-1]));
            end
        end
    endgenerate
endmodule

测试台文件rc_add_sub_tb.v

module RC_ADD_SUB_32_TB;
    reg [`DATA_INDEX_LIMIT:0] A;
    reg [`DATA_INDEX_LIMIT:0] B;
    reg SnA;

    wire [`DATA_INDEX_LIMIT:0] Y;
    wire CO;

    RC_ADD_SUB_32 obj(Y, CO, A, B, SnA);

    initial
    begin
        #5 A = 0; B= 0; SnA = 0;
        #5 A = 0; B= 0; SnA = 1;
        #5 A = 0; B= 1; SnA = 0;
        #5 A = 0; B= 1; SnA = 1;
        #5 A = 1; B= 0; SnA = 0;
        #5 A = 1; B= 0; SnA = 1;
        #5 A = 1; B= 1; SnA = 0;
        #5 A = 1; B= 1; SnA = 1;
        #5;
    end
endmodule 

Answer 1

条件语句有

begin:

，没有标签。事实上，模拟器要么将其视为空白标签，要么将其换行并将 FULL_ADDER 作为标签名称。两者都是非法的。添加标签（首选）或去掉冒号。

仅供参考，

if(i!=31 && i!=0)

是不必要的，因为条件已在先前条件中捕获。

带有标签的示例：

if(i==0) 
begin: gen_first
    FULL_ADDER inst(.S(Y[i]), .CO(CO_TO_CI[i]), .A(A[i]), .B(XOR_OUT[i]), .CI(SnA));
end
else if(i==31) 
begin: gen_last
    FULL_ADDER inst(.S(Y[i]), .CO(CO), .A(A[i]), .B(XOR_OUT[i]), .CI(CO_TO_CI[i-1]));
end
else 
begin: gen_middle
    FULL_ADDER inst(.S(Y[i]), .CO(CO_TO_CI[i]), .A(A[i]), .B(XOR_OUT[i]), .CI(CO_TO_CI[i-1]));
end

或不带标签：

if(i==0) 
begin
    FULL_ADDER inst(.S(Y[i]), .CO(CO_TO_CI[i]), .A(A[i]), .B(XOR_OUT[i]), .CI(SnA));
end
else if(i==31) 
begin
    FULL_ADDER inst(.S(Y[i]), .CO(CO), .A(A[i]), .B(XOR_OUT[i]), .CI(CO_TO_CI[i-1]));
end
else 
begin
    FULL_ADDER inst(.S(Y[i]), .CO(CO_TO_CI[i]), .A(A[i]), .B(XOR_OUT[i]), .CI(CO_TO_CI[i-1]));
end