我正在尝试使用 ip 目录中的浮点 ip。我能够成功生成输出产品，但每当我尝试模拟时，我都会收到以下错误：
"xvhdl --incr --relax -prj tb_rrc_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "D:/Vivado_Workarea/rrc_filter/rrc_filter.srcs/sources_1/ip/floating_point_addition/demo_tb/tb_floating_point_addition.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'tb_floating_point_addition'
ERROR: [VRFC 10-2987] 'floating_point_addition' is not compiled in library 'xil_defaultlib' [D:/Vivado_Workarea/rrc_filter/rrc_filter.srcs/sources_1/ip/floating_point_addition/demo_tb/tb_floating_point_addition.vhd:376]
ERROR: [VRFC 10-3782] unit 'tb' ignored due to previous errors [D:/Vivado_Workarea/rrc_filter/rrc_filter.srcs/sources_1/ip/floating_point_addition/demo_tb/tb_floating_point_addition.vhd:80]
INFO: [VRFC 10-3070] VHDL file 'D:/Vivado_Workarea/rrc_filter/rrc_filter.srcs/sources_1/ip/floating_point_addition/demo_tb/tb_floating_point_addition.vhd' ignored due to errors
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-99] Step results log file:'D:/Vivado_Workarea/rrc_filter/rrc_filter.sim/sim_1/behav/xsim/xvhdl.log'
ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'D:/Vivado_Workarea/rrc_filter/rrc_filter.sim/sim_1/behav/xsim/xvhdl.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
我无法理解为什么导入ip时会出现编译错误。
INFO: [VRFC 10-3070] VHDL file 'D:/Vivado_Workarea/rrc_filter/rrc_filter.srcs/sources_1/ip/floating_point_addition/demo_tb/tb_floating_point_addition.vhd' ignored due to errors
../tb_floating_point_addition.vhd'由于错误而被忽略表示您的测试台中存在错误。要继续进一步消除测试台中的错误。