未显示正确的输出

Question

SystemVerilog 中的这些模块和测试平台用于将两位数乘以 3 并给出四位结果；但是，当我模拟它时，它显示 X 作为输出。我检查了我的模块，但找不到任何具体问题。

//////////////////////////////////////////////////////////////////////////////////
// Parinaz Jafaripourbaghali
//22201152
//Section 2
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module half_adder(input wire a, b,
                   output wire s, c);
    assign s = a ^ b;
    assign c = a & b;
endmodule

module OR2input(input wire a, b,
                output wire y);
    assign y = a | b;
endmodule

module fulladder(input wire a, b, cin,
                  output wire s, c);
    wire n0, n1, n2;
    half_adder ha1(a, b, n0, n1);
    half_adder ha2(n0, cin, s, n2);
    OR2input or2in(n2, n1, c);
endmodule
module two_bitAdder(input wire a0, a1, b0, b1, cin,
 output wire s0, s1, c);
 wire c0;
 fulladder fa1(a0, b0, cin, s0, c0);
 fulladder fa2(a1, b1, c0, s1, c);
endmodule

module ripple_carry_adder(
    input [3:0] A,     // 4-bit input A
    input [3:0] B,     // 4-bit input B
    input Cin,         // Carry-in
    output [3:0] S,    // 4-bit sum output
    output Cout        // Carry-out
);

    wire [3:0] carry;  // Array to store carry bits

    // Full adder instances
    fulladder FA0 (.a(A[0]), .b(B[0]), .cin(Cin), .s(S[0]), .c(carry[0]));
    fulladder FA1 (.a(A[1]), .b(B[1]), .cin(carry[0]), .s(S[1]), .c(carry[1]));
    fulladder FA2 (.a(A[2]), .b(B[2]), .cin(carry[1]), .s(S[2]), .c(carry[2]));
    fulladder FA3 (.a(A[3]), .b(B[3]), .cin(carry[2]), .s(S[3]), .c(Cout));

endmodule
module multiply_by_3(
    input [1:0] inp,      // 2-bit input
    output [3:0] oup      // 4-bit output
);

    wire [3:0] middle;    // 4-bit intermediate result from multiplication

    // Left shift operation to multiply by 3
    assign middle = {inp, 1'b0}; // Concatenate inp with a 0 to perform left shift, equivalent to inp * 2

    // Ripple carry adder to add the original 2-bit number with the result of multiplication by 3
    ripple_carry_adder adder(
        .A(inp),              // 2-bit input A
        .B(middle),           // 4-bit intermediate result
        .Cin(1'b0),           // No carry-in for addition
        .S(oup),              // 4-bit sum output
        .Cout()               // Carry-out not used here
    );

endmodule

测试台：

module tb_multiply_by_3;

    // Inputs
    reg [1:0] inp;      // 2-bit input
    // Outputs
    wire [3:0] oup;     // 4-bit output

    // Instantiate the module under test
    multiply_by_3 uut (
        .inp(inp),
        .oup(oup)
    );

    // Stimulus
    initial begin
        // Test input 1: 01
        inp = 2'b01;
        #20; // Wait for the computation
        // Check the result
        if (oup !== 4'b0110) $display("Test 1 failed. Expected: 0110, Got: %b", oup);
        
        // Test input 2: 10
        inp = 2'b10;
        #20; // Wait for the computation
        // Check the result
        if (oup !== 4'b1100) $display("Test 2 failed. Expected: 1100, Got: %b", oup);
        
        // Test input 3: 11
        inp = 2'b11;
        #20; // Wait for the computation
        // Check the result
        if (oup !== 4'b1110) $display("Test 3 failed. Expected: 1110, Got: %b", oup);

        // End simulation
        $finish;
    end

endmodule

我检查了模块并更改了输出，但结果是相同的

Answer 1

由于此编译警告，您会得到未知数：

        .A(inp),              // 2-bit input A
             |
xmelab: *W,CUVMPW : port sizes differ in port connection(2/4) for the instance(tb_multiply_by_3.uut) .

A

输入端口是4位，但

inp

信号只有2位。这意味着

A[3:2]

未被驱动。您需要将这些位驱动到已知值。

您的模拟器应该通知您这一点。看一下你的编译日志。