需要有关计数器电路的 vhdl 代码的帮助

Question

所以我还在学习VHDL Coding。到目前为止，我已经完成了许多单文件设计。这次我正在做一个需要 Hierachy/Components 的电路。我正在努力为此完成代码。任何帮助表示赞赏！

计数器电路

根据问题陈述，我承认我将制作 3 个组件 - Reg、DIV10 和 DIV10K，然后在顶层设计中我必须 实例化一个 DIV10k 和 Reg 实例以及五个 DIV10 实例。

这是我到目前为止编写的代码，老实说，我不确定要采取的方向。顶层的测试平台也可用。

DIV10K 组件

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.NUMERIC_STD.ALL;
    
    entity DIV10K is
        Port (
            CLK : in std_logic;
            RES : in std_logic;
         OF : out std_logic
        
    end DIV10K;
    
    architecture Behavioral of DIV10K is
        signal counter : unsigned(13 downto 0) := (others => '0');
    begin
        process (CLK, RES)
        begin
            if (RES = '1') then
                counter <= (others => '0');
                OF <= '0';
            elsif (rising_edge(CLK)) then
                counter <= counter + 1;
                if (counter = 10000) then
                    OF <= '1';
                    counter <= (others => '0');
                else
                    OF <= '0';
                end if;
            end if;
        end process;
    end Behavioral;

DIV10 组件

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.NUMERIC_STD.ALL;
    
    entity DIV10 is
        Port ( SI : in  STD_LOGIC;
               CE : in  STD_LOGIC;
               RES : in  STD_LOGIC;
               Q : out  STD_LOGIC_VECTOR (3 downto 0);
               OF : out  STD_LOGIC);
    end DIV10;
    
    architecture Behavioral of DIV10 is
        signal count : unsigned(3 downto 0) := (others => '0');
    begin
        process(SI, CE, RES)
        begin
            if RES = '1' then
                count <= (others => '0');
                OF <= '0';
            elsif rising_edge(CE) then
                if count = "1001" then
                    count <= (others => '0');
                    OF <= '1';
                else
                    count <= count + 1;
                    OF <= '0';
                end if;
            end if;
            
            if rising_edge(SI) then
                count <= (others => '0');
                OF <= '0';
            end if;
        end process;
        
        Q <= std_logic_vector(count);
    end Behavioral;

注册

        library IEEE;
        use IEEE.STD_LOGIC_1164.all;
        use IEEE.NUMERIC_STD.all;
        
        entity Register is
            port(
                CLK: in std_logic;
                RESET: in std_logic;
                LD: in std_logic;
                Q1_in: in unsigned(3 downto 0);
                Q2_in: in unsigned(3 downto 0);
                Q3_in: in unsigned(3 downto 0);
                Q4_in: in unsigned(3 downto 0);
                Q5_in: in unsigned(3 downto 0);
                OF: in std_logic;
                Ones: out unsigned(3 downto 0);
                Tens: out unsigned(3 downto 0);
                Hundreds: out unsigned(3 downto 0);
                Thousands: out unsigned(3 downto 0);
                Ten_Thou: out unsigned(3 downto 0)
            );
        end Register;
        
        architecture Behavioral of Register is
            signal Reg: unsigned(19 downto 0);
        begin
            process(CLK, RESET)
            begin
                if RESET = '1' then
                    Reg <= (others => '0');
                elsif rising_edge(CLK) then
                    if LD = '1' then
                        Reg <= Q5_in & Q4_in & Q3_in & Q2_in & Q1_in;
                    end if;
                    if OF = '1' then
                        Ones <= "0000";
                        Tens <= "0000";
                        Hundreds <= "0000";
                        Thousands <= "0000";
                        Ten_Thou <= "0000";
                    else
                        Ones <= Reg(3 downto 0);
                        Tens <= Reg(7 downto 4);
                        Hundreds <= Reg(11 downto 8);
                        Thousands <= Reg(15 downto 12);
                        Ten_Thou <= Reg(19 downto 16);
                    end if;
                end if;
            end process;
        end Behavioral;

顶层设计

library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.NUMERIC_STD.ALL;
    
    entity Freq_Counter is
        Port ( CLK: in std_logic;
               RES: in std_logic;
               SI: in std_logic;
               Ones: out std_logic_vector(3 downto 0);
               Tens: out std_logic_vector(3 downto 0);
               Hundreds: out std_logic_vector(3 downto 0);
               Thousands: out std_logic_vector(3 downto 0);
               Ten_Thou: out std_logic_vector(3 downto 0));
    end Freq_Counter;
    
    architecture Behavioral of Freq_Counter is
    
        -- Component declarations
        component DIV10
            Port ( CE, RES: in std_logic;
                   SI: in std_logic;
                   Q: out std_logic_vector(3 downto 0);
                   OF: out std_logic);
        end component;
    
        component DIV10K
            Port ( CLK, RES: in std_logic;
                   OF: out std_logic);
        end component;
    
        component Register
            Port ( CLK, RES, LD: in std_logic;
                   Q1_in, Q2_in, Q3_in, Q4_in, Q5_in: in std_logic_vector(3 downto 0);
                   Ones, Tens, Hundreds, Thousands, Ten_Thou: out std_logic_vector(3 downto 0));
        end component;
    
        -- Signal declarations
        signal Q1, Q2, Q3, Q4, Q5: std_logic_vector(3 downto 0);
        signal OF1, OF2, OF3, OF4, OF5, OF: std_logic;
        signal LD: std_logic;
    
    begin
    
        -- Component instantiations
        DIV10K_inst: DIV10K port map (CLK => CLK, RES => RES, OF => OF);
    
        DIV10_1_inst: DIV10 port map (CE => '1', RES => RES, SI => SI, Q => Q1, OF => OF1);
        DIV10_2_inst: DIV10 port map (CE => OF1, RES => RES, SI => '0', Q => Q2, OF => OF2);
        DIV10_3_inst: DIV10 port map (CE => OF2, RES => RES, SI => '0', Q => Q3, OF => OF3);
        DIV10_4_inst: DIV10 port map (CE => OF3, RES => RES, SI => '0', Q => Q4, OF => OF4);
        DIV10_5_inst: DIV10 port map (CE => OF4, RES => RES, SI => '0', Q => Q5, OF => OF5);
    
        Register_inst: Register port map (CLK => CLK, RES => RES, LD => LD,
                                          Q1_in => Q1, Q2_in => Q2, Q3_in => Q3, Q4_in => Q4, Q5_in => Q5,
                                          Ones => Ones, Tens => Tens, Hundreds => Hundreds, Thousands => Thousands, Ten_Thou => Ten_Thou);
    
        -- Output logic
        LD <= OF;
    
    end Behavioral;