VHDL分量多路复用器在modelsim中不返回值

Question

我正在尝试使用带端口映射的加法器，mux2和mux4组件制作ALU。我已经编写了ALU，它通过编译即可。问题是，当我尝试在modelsim中给出值时，加法器工作正常，但mux2（sub_module）和mux4（sub_module x2）没有给出输出。我替换了2-3倍的多路复用器代码，问题是相同的。我只得到outY的UUUUUUUU值。我已将代码最小化。

ModelSim

最小化主ALU

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ALU7_minimal is
    Port ( inpA : IN STD_LOGIC_VECTOR (7 downto 0) :="10110001";
             inpB : IN STD_LOGIC_VECTOR (7 downto 0) :="00011001";
        ALUS0 : in  STD_LOGIC := '0';
            outY : out  STD_LOGIC_VECTOR (7 downto 0));
end ALU7_minimal;

architecture Behavioral  of ALU7_minimal is

component sub_module
port(x,y : in STD_LOGIC_VECTOR (7 downto 0);
s: in STD_LOGIC;
z: out STD_LOGIC_VECTOR (7 downto 0));
end component;


begin

U0: sub_module port map (inpA, inpB, ALUS0, outY );


end Behavioral ;

mux2-1

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity sub_module is
port(x,y : in STD_LOGIC_VECTOR (7 downto 0);
s: in STD_LOGIC;
z: out STD_LOGIC_VECTOR (7 downto 0));
end sub_module ;

architecture Behavioral of sub_module is

begin

process (x,y,s) is
begin
if (s ='0') then
z <= x;
else
z <= y;
end if;
end process;

end Behavioral;

Answer 1

不需要处理！

begin
with s select
    z <= x  when '0',
         y  when '1',
        'U' when others;