错误 (10170)：Verilog HDL 语法错误 (59) 靠近文本：“posedge”；期待一个操作数

Question

我在第 59 行遇到错误。我尝试用 Google 搜索，但找不到任何内容这是我的代码：

always @(posedge clk or negedge nReset) begin
    if (minute_start_in == 1'b1) begin
        counter <= 0;
    end else if (nReset == 1'b0) begin
        counter <= 0;
        dcf_values <= 59'b0;
    end else if (posedge(clk) && (clk_en_1hz == 1'b1)) begin // Line 59
        dcf_values[counter] <= ~dcf_Signal_in;
        counter <= counter + 1;
    end;
end

Answer 1

您需要重组代码，以便

nReset

具有优先权。

always @(posedge clk or negedge nReset)
    if (nReset == 1'b0) begin
        counter <= 0;
        dcf_values <= 59'b0;
    end else // must have been triggered by posedge clk
    if (minute_start_in == 1'b1) begin
        counter <= 0;
    end else if (clk_en_1hz == 1'b1)) begin 
        dcf_values[counter] <= ~dcf_Signal_in;
        counter <= counter + 1;
    end