我正在尝试构建一个 ALU,我想用循环来测试它,问题是我有单独的
std_logic
输入,对于循环我需要一个输入向量。
我尝试使用变量创建输入向量,但出现此错误:[XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received.
我不知道这个错误意味着什么,这是我的测试台:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity TB_ALU is
-- Port ( );
end TB_ALU;
architecture Behavioral of TB_ALU is
component ALU is
Port ( INVA, A, ENA, B, ENB, cin, f1, f0: in STD_LOGIC;
cout : buffer STD_LOGIC;
output : out STD_LOGIC);
end component;
signal INVA, A, ENA, B, ENB, cin, output, cout, f1, f0 : STD_LOGIC;
begin
U2: ALU port map (INVA=>INVA, A=>A, ENA=>ENA, B=>B, ENB=>ENB, cin=>cin, f1=>f1, f0=>f0, output=>output, cout=>cout);
process
variable input : std_logic_vector(5 downto 0):=(f1, f0, ena, enb, inva, cin);
begin
wait for 10ns;
a<='1'; b<='1';
lp: for i in 0 to 63 loop
input := std_logic_vector(to_unsigned(i,6));
WAIT FOR 10ns;
end loop lp;
wait;
end process;
end Behavioral;
10
和 ns
之间应该有空格(出现 2 次)。但是您的代码在循环中修改变量而没有任何明显的副作用,实际上没有任何意义。如果您的目标是生成 6 个信号的全部 64 种组合,并在它们之间有 10 ns
暂停,请尝试:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_alu is
end entity tb_alu;
architecture behavioral of tb_alu is
component alu is
port(inva, a, ena, b, enb, cin, f1, f0: in std_ulogic;
cout: buffer std_ulogic;
output: out std_ulogic);
end component;
signal inva, a, ena, b, enb, cin, output, cout, f1, f0: std_ulogic;
begin
u2: alu
port map(inva => inva, a => a, ena => ena, b => b, enb => enb, cin => cin, f1 => f1, f0 => f0, output => output, cout => cout);
process
begin
wait for 10 ns;
a<='1';
b<='1';
lp: for i in 0 to 63 loop
(f1, f0, ena, enb, inva, cin) <= std_ulogic_vector(to_unsigned(i,6));
wait for 10 ns;
end loop lp;
wait;
end process;
end behavioral;
左侧信号聚合的简单示例。
注意将所有
std_logic
替换为 std_ulogic
(只要您不知道区别,就始终使用 std_ulogic
,而不是 std_logic
)。