System Verilog 使用流运算符连接动态数组的所有元素

Question

我想连接动态数组的所有元素，并将整个数组左移 8 位。下面的代码适用于固定且已知的数组大小。如何将流式运算符与动态数组连接？

module tb;
    bit [511:0] payload[3];
    bit [(512*payload.size()-1):0] stream, concat;
    bit [(520*payload.size()-1):0] shift_stream; 

    initial begin
              payload[0]='he2f784c5e33724c67cfde9f9462df78c76d457ed1e8dcd3d3b23f17606d7cd0d00f3e30189375212b2c2846546df998d06b97b0db1f056638484fdadedadadad;
   payload[1]='hc03b22800573870ab1ef6263b2a7266596ab582dde8e28bd2e58495ce2ca4ec5f4007ae8e77696ce793069f247ecdb8f8932d612bbd2727772aff7aaaaaaaaaa;
   payload[2]='he5730aca0509650a11844923e7c572cf0effe91dd7563eae81174a02eaa62ad5359fdd6ba9a7d65386bc380d8983b813cb203e96cecccc9d557845eeeeeeeeee;

       foreach(payload[i]) begin *//How to use loop for dynamic streaming concatenation?*
          concat = {>>{payload[i]}}; **//Incorrect!! How to do this?**
          $display("concat = 0x%h", concat);      
       end
       stream = {>>{payload[2], payload[1],payload[0]}}; //This works but what if payload size is unknown
       $display("stream = 0x%h", stream);
       shift_stream = {stream, 8'h0};
       $display("stream = 0x%h", shift_stream);
    end
 endmodule

我尝试使用固定数组大小 3。对于动态数组如何做到这一点？

Answer 1

你可以做

stream = {<<512{payload}};

或

foreach(payload[i])
  stream[i*512+:512] = payload[i];